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[AARCH64] Add FEAT_SSVE_FEXPA and fix unsupported features list (#134368)
This patch adds new feature introduced in [2025-03 release](https://developer.arm.com/documentation/ddi0602/2025-03/SVE-Instructions/FEXPA--Floating-point-exponential-accelerator-) and changes feature requirements for fexpa instructions and intrinsics. Additionally it fixes unsupported features list by moving fearures dependent on sme2p1 to correct location.
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-16
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9 files changed

+34
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‎clang/include/clang/Basic/arm_sve.td

+4-2
Original file line numberDiff line numberDiff line change
@@ -836,9 +836,11 @@ defm SVRINTP : SInstZPZ<"svrintp", "hfd", "aarch64_sve_frintp">;
836836
defm SVRINTX : SInstZPZ<"svrintx", "hfd", "aarch64_sve_frintx">;
837837
defm SVRINTZ : SInstZPZ<"svrintz", "hfd", "aarch64_sve_frintz">;
838838
defm SVSQRT : SInstZPZ<"svsqrt", "hfd", "aarch64_sve_fsqrt">;
839-
839+
def SVEXPA : SInst<"svexpa[_{d}]", "du", "hfd", MergeNone, "aarch64_sve_fexpa_x", [VerifyRuntimeMode]>{
840+
let SVETargetGuard = "sve";
841+
let SMETargetGuard = "sme2,ssve-fexpa";
842+
}
840843
let SVETargetGuard = "sve", SMETargetGuard = InvalidMode in {
841-
def SVEXPA : SInst<"svexpa[_{d}]", "du", "hfd", MergeNone, "aarch64_sve_fexpa_x">;
842844
def SVTMAD : SInst<"svtmad[_{d}]", "dddi", "hfd", MergeNone, "aarch64_sve_ftmad_x", [], [ImmCheck<2, ImmCheck0_7>]>;
843845
def SVTSMUL : SInst<"svtsmul[_{d}]", "ddu", "hfd", MergeNone, "aarch64_sve_ftsmul_x">;
844846
def SVTSSEL : SInst<"svtssel[_{d}]", "ddu", "hfd", MergeNone, "aarch64_sve_ftssel_x">;

‎clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_expa.c

+11-3
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,12 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
22
// REQUIRES: aarch64-registered-target
33
// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s
4+
// RUN: %clang_cc1 -triple aarch64 -target-feature +ssve-fexpa -target-feature +sme2 -target-feature +sme -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s
45
// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
56
// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s
67
// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
78
// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
9+
// RUN: %clang_cc1 -triple aarch64 -target-feature +ssve-fexpa -target-feature +sme2 -target-feature +sme -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
810
#include <arm_sve.h>
911

1012
#ifdef SVE_OVERLOADED_FORMS
@@ -14,6 +16,12 @@
1416
#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
1517
#endif
1618

19+
#ifdef __ARM_FEATURE_SME
20+
#define STREAMING __arm_streaming
21+
#else
22+
#define STREAMING
23+
#endif
24+
1725
// CHECK-LABEL: @test_svexpa_f16(
1826
// CHECK-NEXT: entry:
1927
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.fexpa.x.nxv8f16(<vscale x 8 x i16> [[OP:%.*]])
@@ -24,7 +32,7 @@
2432
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.fexpa.x.nxv8f16(<vscale x 8 x i16> [[OP:%.*]])
2533
// CPP-CHECK-NEXT: ret <vscale x 8 x half> [[TMP0]]
2634
//
27-
svfloat16_t test_svexpa_f16(svuint16_t op)
35+
svfloat16_t test_svexpa_f16(svuint16_t op) STREAMING
2836
{
2937
return SVE_ACLE_FUNC(svexpa,_f16,,)(op);
3038
}
@@ -39,7 +47,7 @@ svfloat16_t test_svexpa_f16(svuint16_t op)
3947
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.fexpa.x.nxv4f32(<vscale x 4 x i32> [[OP:%.*]])
4048
// CPP-CHECK-NEXT: ret <vscale x 4 x float> [[TMP0]]
4149
//
42-
svfloat32_t test_svexpa_f32(svuint32_t op)
50+
svfloat32_t test_svexpa_f32(svuint32_t op) STREAMING
4351
{
4452
return SVE_ACLE_FUNC(svexpa,_f32,,)(op);
4553
}
@@ -54,7 +62,7 @@ svfloat32_t test_svexpa_f32(svuint32_t op)
5462
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sve.fexpa.x.nxv2f64(<vscale x 2 x i64> [[OP:%.*]])
5563
// CPP-CHECK-NEXT: ret <vscale x 2 x double> [[TMP0]]
5664
//
57-
svfloat64_t test_svexpa_f64(svuint64_t op)
65+
svfloat64_t test_svexpa_f64(svuint64_t op) STREAMING
5866
{
5967
return SVE_ACLE_FUNC(svexpa,_f64,,)(op);
6068
}

‎clang/test/Driver/print-supported-extensions-aarch64.c

+1
Original file line numberDiff line numberDiff line change
@@ -81,6 +81,7 @@
8181
// CHECK-NEXT: ssbs FEAT_SSBS, FEAT_SSBS2 Enable Speculative Store Bypass Safe bit
8282
// CHECK-NEXT: ssve-aes FEAT_SSVE_AES Enable Armv9.6-A SVE AES support in streaming SVE mode
8383
// CHECK-NEXT: ssve-bitperm FEAT_SSVE_BitPerm Enable Armv9.6-A SVE BitPerm support in streaming SVE mode
84+
// CHECK-NEXT: ssve-fexpa FEAT_SSVE_FEXPA Enable SVE FEXPA instruction in Streaming SVE mode
8485
// CHECK-NEXT: ssve-fp8dot2 FEAT_SSVE_FP8DOT2 Enable SVE2 FP8 2-way dot product instructions
8586
// CHECK-NEXT: ssve-fp8dot4 FEAT_SSVE_FP8DOT4 Enable SVE2 FP8 4-way dot product instructions
8687
// CHECK-NEXT: ssve-fp8fma FEAT_SSVE_FP8FMA Enable SVE2 FP8 multiply-add instructions

‎llvm/lib/Target/AArch64/AArch64.td

+5-4
Original file line numberDiff line numberDiff line change
@@ -74,13 +74,14 @@ def SVEUnsupported : AArch64Unsupported {
7474
}
7575

7676
let F = [HasSME2p2, HasSVE2p2_or_SME2p2, HasNonStreamingSVE_or_SME2p2,
77-
HasNonStreamingSVE2p2_or_SME2p2, HasNonStreamingSVE2_or_SSVE_BitPerm,
78-
HasSME_MOP4, HasSME_TMOP] in
77+
HasNonStreamingSVE2p2_or_SME2p2] in
7978
def SME2p2Unsupported : AArch64Unsupported;
8079

8180
def SME2p1Unsupported : AArch64Unsupported {
82-
let F = !listconcat([HasSME2p1, HasSVE2p1_or_SME2p1, HasNonStreamingSVE2p1_or_SSVE_AES],
83-
SME2p2Unsupported.F);
81+
let F = !listconcat([HasSME2p1, HasSVE2p1_or_SME2p1, HasNonStreamingSVE2p1_or_SSVE_AES,
82+
HasSME_MOP4, HasSME_TMOP, HasNonStreamingSVE_or_SSVE_FEXPA,
83+
HasNonStreamingSVE2_or_SSVE_BitPerm],
84+
SME2p2Unsupported.F);
8485
}
8586

8687
def SME2Unsupported : AArch64Unsupported {

‎llvm/lib/Target/AArch64/AArch64Features.td

+3-1
Original file line numberDiff line numberDiff line change
@@ -576,7 +576,9 @@ def FeatureSME_MOP4: ExtensionWithMArch<"sme-mop4", "SME_MOP4", "FEAT_SME_MOP4",
576576
def FeatureSME_TMOP: ExtensionWithMArch<"sme-tmop", "SME_TMOP", "FEAT_SME_TMOP",
577577
"Enable SME Structured sparsity outer product instructions.", [FeatureSME2]>;
578578

579-
//===----------------------------------------------------------------------===//
579+
def FeatureSSVE_FEXPA : ExtensionWithMArch<"ssve-fexpa", "SSVE_FEXPA", "FEAT_SSVE_FEXPA",
580+
"Enable SVE FEXPA instruction in Streaming SVE mode", [FeatureSME2]>;
581+
580582
// Other Features
581583
//===----------------------------------------------------------------------===//
582584

‎llvm/lib/Target/AArch64/AArch64InstrInfo.td

+4
Original file line numberDiff line numberDiff line change
@@ -294,6 +294,10 @@ def HasNonStreamingSVE2_or_SSVE_BitPerm
294294
: Predicate<"(Subtarget->isSVEAvailable() && Subtarget->hasSVE2()) ||"
295295
"(Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSSVE_BitPerm())">,
296296
AssemblerPredicateWithAll<(any_of FeatureSVE2, FeatureSSVE_BitPerm), "sve2 or ssve-bitperm">;
297+
def HasNonStreamingSVE_or_SSVE_FEXPA
298+
: Predicate<"(Subtarget->isSVEAvailable() && Subtarget->hasSVE()) ||"
299+
"(Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSSVE_FEXPA())">,
300+
AssemblerPredicateWithAll<(any_of FeatureSVE, FeatureSSVE_FEXPA), "sve or ssve-fexpa">;
297301

298302
// A subset of NEON instructions are legal in Streaming SVE execution mode,
299303
// so don't need the additional check for 'isNeonAvailable'.

‎llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

+1-1
Original file line numberDiff line numberDiff line change
@@ -980,7 +980,7 @@ let Predicates = [HasSVE_or_SME] in {
980980
def MOVPRFX_ZZ : sve_int_bin_cons_misc_0_c<0b00000001, "movprfx", ZPRAny>;
981981
} // End HasSVE_or_SME
982982

983-
let Predicates = [HasNonStreamingSVE_or_SME2p2] in {
983+
let Predicates = [HasNonStreamingSVE_or_SSVE_FEXPA] in {
984984
defm FEXPA_ZZ : sve_int_bin_cons_misc_0_c_fexpa<"fexpa", int_aarch64_sve_fexpa_x>;
985985
} // End HasSVE
986986

‎llvm/test/CodeGen/AArch64/sve-intrinsics-fexpa.ll

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
3-
; RUN: llc -mtriple=aarch64-linux-gnu -force-streaming -mattr=+sme2p2 < %s | FileCheck %s
3+
; RUN: llc -mtriple=aarch64-linux-gnu -force-streaming -mattr=+ssve-fexpa < %s | FileCheck %s
44

55
define <vscale x 8 x half> @fexpa_h(<vscale x 8 x i16> %a) {
66
; CHECK-LABEL: fexpa_h:

‎llvm/test/MC/AArch64/SVE/fexpa.s

+4-4
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
22
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
3-
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \
3+
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+ssve-fexpa < %s \
44
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
55
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
66
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
@@ -14,17 +14,17 @@
1414
fexpa z0.h, z31.h
1515
// CHECK-INST: fexpa z0.h, z31.h
1616
// CHECK-ENCODING: [0xe0,0xbb,0x60,0x04]
17-
// CHECK-ERROR: instruction requires: sve or sme2p2
17+
// CHECK-ERROR: instruction requires: sve or ssve-fexpa
1818
// CHECK-UNKNOWN: 0460bbe0 <unknown>
1919

2020
fexpa z0.s, z31.s
2121
// CHECK-INST: fexpa z0.s, z31.s
2222
// CHECK-ENCODING: [0xe0,0xbb,0xa0,0x04]
23-
// CHECK-ERROR: instruction requires: sve or sme2p2
23+
// CHECK-ERROR: instruction requires: sve or ssve-fexpa
2424
// CHECK-UNKNOWN: 04a0bbe0 <unknown>
2525

2626
fexpa z0.d, z31.d
2727
// CHECK-INST: fexpa z0.d, z31.d
2828
// CHECK-ENCODING: [0xe0,0xbb,0xe0,0x04]
29-
// CHECK-ERROR: instruction requires: sve or sme2p2
29+
// CHECK-ERROR: instruction requires: sve or ssve-fexpa
3030
// CHECK-UNKNOWN: 04e0bbe0 <unknown>

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