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[NFC] Added tests for D64285
llvm-svn: 365501
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‎llvm/test/Transforms/InstSimplify/ashr-lshr.ll

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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -instcombine -S | FileCheck %s
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define i32 @ashr_lshr_abs(i32 %x, i32 %y) {
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; CHECK-LABEL: @ashr_lshr_abs(
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; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: ret i32 [[R]]
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;
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%cmp = icmp sge i32 %x, 0
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%l = lshr i32 %x, %y
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%r = ashr i32 %x, %y
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%ret = select i1 %cmp, i32 %l, i32 %r
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ret i32 %ret
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}
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define i32 @ashr_lshr_abs_both_exact(i32 %x, i32 %y) {
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; CHECK-LABEL: @ashr_lshr_abs(
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; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: ret i32 [[R]]
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;
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%cmp = icmp sge i32 %x, 0
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%l = lshr exact i32 %x, %y
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%r = ashr exact i32 %x, %y
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%ret = select i1 %cmp, i32 %l, i32 %r
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ret i32 %ret
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}
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define i32 @ashr_lshr_abs2(i32 %x, i32 %y) {
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; CHECK-LABEL: @ashr_lshr_abs2(
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; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: ret i32 [[R]]
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;
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%cmp = icmp sgt i32 %x, -1
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%l = lshr i32 %x, %y
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%r = ashr i32 %x, %y
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%ret = select i1 %cmp, i32 %l, i32 %r
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ret i32 %ret
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}
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define <2 x i32> @ashr_lshr_abs_vec(<2 x i32> %x, <2 x i32> %y) {
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; CHECK-LABEL: @ashr_lshr_abs_vec(
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; CHECK-NEXT: [[R:%.*]] = ashr <2 x i32> [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: ret <2 x i32> [[R]]
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;
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%cmp = icmp sge <2 x i32> %x, zeroinitializer
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%l = lshr <2 x i32> %x, %y
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%r = ashr <2 x i32> %x, %y
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%ret = select <2 x i1> %cmp, <2 x i32> %l, <2 x i32> %r
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ret <2 x i32> %ret
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}
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define i32 @ashr_lshr_nabs2(i32 %x, i32 %y) {
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; CHECK-LABEL: @ashr_lshr_nabs2(
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; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: ret i32 [[R]]
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;
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%cmp = icmp sle i32 %x, 0
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%l = lshr i32 %x, %y
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%r = ashr i32 %x, %y
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%ret = select i1 %cmp, i32 %r, i32 %l
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ret i32 %ret
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}
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define i32 @ashr_lshr_nabs(i32 %x, i32 %y) {
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; CHECK-LABEL: @ashr_lshr_nabs(
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; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: ret i32 [[R]]
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;
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%cmp = icmp slt i32 %x, 1
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%l = lshr i32 %x, %y
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%r = ashr i32 %x, %y
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%ret = select i1 %cmp, i32 %r, i32 %l
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ret i32 %ret
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}
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define <2 x i32> @ashr_lshr_nabs_vec(<2 x i32> %x, <2 x i32> %y) {
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; CHECK-LABEL: @ashr_lshr_nabs_vec(
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; CHECK-NEXT: [[R:%.*]] = ashr <2 x i32> [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: ret <2 x i32> [[R]]
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;
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%cmp = icmp sle <2 x i32> %x, zeroinitializer
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%l = lshr <2 x i32> %x, %y
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%r = ashr <2 x i32> %x, %y
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%ret = select <2 x i1> %cmp, <2 x i32> %r, <2 x i32> %l
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ret <2 x i32> %ret
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}
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; Negative tests
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define i32 @ashr_lshr_wrong_abs(i32 %x, i32 %y) {
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; CHECK-LABEL: @ashr_lshr_wrong_abs(
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; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -2
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; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
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; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X]], [[Y]]
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; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
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; CHECK-NEXT: ret i32 [[RET]]
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;
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%cmp = icmp sge i32 %x, -1
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%l = lshr i32 %x, %y
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%r = ashr i32 %x, %y
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%ret = select i1 %cmp, i32 %l, i32 %r
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ret i32 %ret
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}
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define i32 @ashr_lshr_abs_shift_wrong_pred(i32 %x, i32 %y, i32 %z) {
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; CHECK-LABEL: @ashr_lshr_abs_shift_wrong_pred(
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; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 1
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; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
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; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X]], [[Y]]
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; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
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; CHECK-NEXT: ret i32 [[RET]]
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;
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%cmp = icmp sle i32 %x, 0
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%l = lshr i32 %x, %y
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%r = ashr i32 %x, %y
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%ret = select i1 %cmp, i32 %l, i32 %r
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ret i32 %ret
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}
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define i32 @ashr_lshr_abs_shift_wrong_pred2(i32 %x, i32 %y, i32 %z) {
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; CHECK-LABEL: @ashr_lshr_abs_shift_wrong_pred2(
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; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[Z:%.*]], -1
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; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X]], [[Y]]
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; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
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; CHECK-NEXT: ret i32 [[RET]]
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;
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%cmp = icmp sge i32 %z, 0
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%l = lshr i32 %x, %y
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%r = ashr i32 %x, %y
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%ret = select i1 %cmp, i32 %l, i32 %r
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ret i32 %ret
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}
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define i32 @ashr_lshr_abs_wrong_operands(i32 %x, i32 %y) {
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; CHECK-LABEL: @ashr_lshr_abs_wrong_operands(
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; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
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; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
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; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X]], [[Y]]
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; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[R]], i32 [[L]]
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; CHECK-NEXT: ret i32 [[RET]]
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;
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%cmp = icmp sge i32 %x, 0
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%l = lshr i32 %x, %y
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%r = ashr i32 %x, %y
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%ret = select i1 %cmp, i32 %r, i32 %l
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ret i32 %ret
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}
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define i32 @ashr_lshr_abs_no_ashr(i32 %x, i32 %y) {
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; CHECK-LABEL: @ashr_lshr_abs_no_ashr(
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; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
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; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
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; CHECK-NEXT: [[R:%.*]] = xor i32 [[X]], [[Y]]
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; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
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; CHECK-NEXT: ret i32 [[RET]]
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;
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%cmp = icmp sge i32 %x, 0
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%l = lshr i32 %x, %y
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%r = xor i32 %x, %y
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%ret = select i1 %cmp, i32 %l, i32 %r
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ret i32 %ret
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}
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define i32 @ashr_lshr_abs_shift_amt_mismatch(i32 %x, i32 %y, i32 %z) {
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; CHECK-LABEL: @ashr_lshr_abs_shift_amt_mismatch(
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; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
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; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
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; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X]], [[Z:%.*]]
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; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
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; CHECK-NEXT: ret i32 [[RET]]
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;
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%cmp = icmp sge i32 %x, 0
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%l = lshr i32 %x, %y
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%r = ashr i32 %x, %z
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%ret = select i1 %cmp, i32 %l, i32 %r
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ret i32 %ret
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}
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define i32 @ashr_lshr_abs_shift_base_mismatch(i32 %x, i32 %y, i32 %z) {
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; CHECK-LABEL: @ashr_lshr_abs_shift_base_mismatch(
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; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
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; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
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; CHECK-NEXT: [[R:%.*]] = ashr i32 [[Z:%.*]], [[Y]]
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; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
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; CHECK-NEXT: ret i32 [[RET]]
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;
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%cmp = icmp sge i32 %x, 0
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%l = lshr i32 %x, %y
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%r = ashr i32 %z, %y
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%ret = select i1 %cmp, i32 %l, i32 %r
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ret i32 %ret
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}
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define i32 @ashr_lshr_abs_no_lshr(i32 %x, i32 %y) {
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; CHECK-LABEL: @ashr_lshr_abs_no_lshr(
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; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
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; CHECK-NEXT: [[L:%.*]] = add i32 [[X]], [[Y:%.*]]
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; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X]], [[Y]]
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; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
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; CHECK-NEXT: ret i32 [[RET]]
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;
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%cmp = icmp sge i32 %x, 0
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%l = add i32 %x, %y
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%r = ashr i32 %x, %y
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%ret = select i1 %cmp, i32 %l, i32 %r
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ret i32 %ret
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}
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define <2 x i32> @ashr_lshr_abs_vec_wrong_pred(<2 x i32> %x, <2 x i32> %y) {
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; CHECK-LABEL: @ashr_lshr_abs_vec_wrong_pred(
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; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i32> [[X:%.*]], <i32 1, i32 1>
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; CHECK-NEXT: [[L:%.*]] = lshr <2 x i32> [[X]], [[Y:%.*]]
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; CHECK-NEXT: [[R:%.*]] = ashr <2 x i32> [[X]], [[Y]]
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; CHECK-NEXT: [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[L]], <2 x i32> [[R]]
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; CHECK-NEXT: ret <2 x i32> [[RET]]
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;
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%cmp = icmp sle <2 x i32> %x, zeroinitializer
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%l = lshr <2 x i32> %x, %y
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%r = ashr <2 x i32> %x, %y
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%ret = select <2 x i1> %cmp, <2 x i32> %l, <2 x i32> %r
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ret <2 x i32> %ret
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}
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define <2 x i32> @ashr_lshr_nabs_vec_wrong_pred(<2 x i32> %x, <2 x i32> %y) {
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; CHECK-LABEL: @ashr_lshr_nabs_vec_wrong_pred(
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; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i32> [[X:%.*]], <i32 -1, i32 -1>
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; CHECK-NEXT: [[L:%.*]] = lshr <2 x i32> [[X]], [[Y:%.*]]
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; CHECK-NEXT: [[R:%.*]] = ashr <2 x i32> [[X]], [[Y]]
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; CHECK-NEXT: [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[R]], <2 x i32> [[L]]
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; CHECK-NEXT: ret <2 x i32> [[RET]]
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;
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%cmp = icmp sge <2 x i32> %x, zeroinitializer
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%l = lshr <2 x i32> %x, %y
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%r = ashr <2 x i32> %x, %y
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%ret = select <2 x i1> %cmp, <2 x i32> %r, <2 x i32> %l
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ret <2 x i32> %ret
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}
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