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Revert "[InlineAsm] wrap ConstraintCode in enum class NFC (#66003)"
This reverts commit 2ca4d13. Also revert the followup, "[InlineAsm] fix botched merge conflict resolution" This reverts commit 8b9bf3a. There were SystemZ and Mips build errors, too many to fix forward.
1 parent 2ec7dba commit ee643b7

25 files changed

+170
-187
lines changed

‎llvm/include/llvm/CodeGen/SelectionDAGISel.h

+3-4
Original file line numberDiff line numberDiff line change
@@ -89,10 +89,9 @@ class SelectionDAGISel : public MachineFunctionPass {
8989
/// not match or is not implemented, return true. The resultant operands
9090
/// (which will appear in the machine instruction) should be added to the
9191
/// OutOps vector.
92-
virtual bool
93-
SelectInlineAsmMemoryOperand(const SDValue &Op,
94-
InlineAsm::ConstraintCode ConstraintID,
95-
std::vector<SDValue> &OutOps) {
92+
virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
93+
unsigned ConstraintID,
94+
std::vector<SDValue> &OutOps) {
9695
return true;
9796
}
9897

‎llvm/include/llvm/CodeGen/TargetLowering.h

+6-7
Original file line numberDiff line numberDiff line change
@@ -4833,17 +4833,16 @@ class TargetLowering : public TargetLoweringBase {
48334833
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
48344834
StringRef Constraint, MVT VT) const;
48354835

4836-
virtual InlineAsm::ConstraintCode
4837-
getInlineAsmMemConstraint(StringRef ConstraintCode) const {
4836+
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const {
48384837
if (ConstraintCode == "m")
4839-
return InlineAsm::ConstraintCode::m;
4838+
return InlineAsm::Constraint_m;
48404839
if (ConstraintCode == "o")
4841-
return InlineAsm::ConstraintCode::o;
4840+
return InlineAsm::Constraint_o;
48424841
if (ConstraintCode == "X")
4843-
return InlineAsm::ConstraintCode::X;
4842+
return InlineAsm::Constraint_X;
48444843
if (ConstraintCode == "p")
4845-
return InlineAsm::ConstraintCode::p;
4846-
return InlineAsm::ConstraintCode::Unknown;
4844+
return InlineAsm::Constraint_p;
4845+
return InlineAsm::Constraint_Unknown;
48474846
}
48484847

48494848
/// Try to replace an X constraint, which matches anything, with another that

‎llvm/include/llvm/IR/InlineAsm.h

+78-78
Original file line numberDiff line numberDiff line change
@@ -217,6 +217,48 @@ class InlineAsm final : public Value {
217217
Extra_MayLoad = 8,
218218
Extra_MayStore = 16,
219219
Extra_IsConvergent = 32,
220+
221+
// Memory constraint codes.
222+
// These could be tablegenerated but there's little need to do that since
223+
// there's plenty of space in the encoding to support the union of all
224+
// constraint codes for all targets.
225+
// Addresses are included here as they need to be treated the same by the
226+
// backend, the only difference is that they are not used to actaully
227+
// access memory by the instruction.
228+
// TODO: convert to enum?
229+
Constraint_Unknown = 0,
230+
Constraint_es,
231+
Constraint_i,
232+
Constraint_k,
233+
Constraint_m,
234+
Constraint_o,
235+
Constraint_v,
236+
Constraint_A,
237+
Constraint_Q,
238+
Constraint_R,
239+
Constraint_S,
240+
Constraint_T,
241+
Constraint_Um,
242+
Constraint_Un,
243+
Constraint_Uq,
244+
Constraint_Us,
245+
Constraint_Ut,
246+
Constraint_Uv,
247+
Constraint_Uy,
248+
Constraint_X,
249+
Constraint_Z,
250+
Constraint_ZB,
251+
Constraint_ZC,
252+
Constraint_Zy,
253+
254+
// Address constraints
255+
Constraint_p,
256+
Constraint_ZQ,
257+
Constraint_ZR,
258+
Constraint_ZS,
259+
Constraint_ZT,
260+
261+
Constraints_Max = Constraint_ZT,
220262
};
221263

222264
// Inline asm operands map to multiple SDNode / MachineInstr operands.
@@ -232,46 +274,6 @@ class InlineAsm final : public Value {
232274
Func = 7, // Address operand of function call
233275
};
234276

235-
// Memory constraint codes.
236-
// Addresses are included here as they need to be treated the same by the
237-
// backend, the only difference is that they are not used to actaully
238-
// access memory by the instruction.
239-
enum class ConstraintCode : uint32_t {
240-
Unknown = 0,
241-
es,
242-
i,
243-
k,
244-
m,
245-
o,
246-
v,
247-
A,
248-
Q,
249-
R,
250-
S,
251-
T,
252-
Um,
253-
Un,
254-
Uq,
255-
Us,
256-
Ut,
257-
Uv,
258-
Uy,
259-
X,
260-
Z,
261-
ZB,
262-
ZC,
263-
Zy,
264-
265-
// Address constraints
266-
p,
267-
ZQ,
268-
ZR,
269-
ZS,
270-
ZT,
271-
272-
Max = ZT,
273-
};
274-
275277
// These are helper methods for dealing with flags in the INLINEASM SDNode
276278
// in the backend.
277279
//
@@ -373,14 +375,11 @@ class InlineAsm final : public Value {
373375
return true;
374376
}
375377

376-
ConstraintCode getMemoryConstraintID() const {
378+
// TODO: convert to enum?
379+
unsigned getMemoryConstraintID() const {
377380
assert((isMemKind() || isFuncKind()) &&
378381
"Not expected mem or function flag!");
379-
uint32_t D = getData();
380-
assert(D < static_cast<uint32_t>(ConstraintCode::Max) &&
381-
D >= static_cast<uint32_t>(ConstraintCode::Unknown) &&
382-
"unexpected value for memory constraint");
383-
return static_cast<ConstraintCode>(D);
382+
return getData();
384383
}
385384

386385
/// setMatchingOp - Augment an existing flag with information indicating
@@ -404,11 +403,12 @@ class InlineAsm final : public Value {
404403

405404
/// setMemConstraint - Augment an existing flag with the constraint code for
406405
/// a memory constraint.
407-
void setMemConstraint(ConstraintCode C) {
406+
void setMemConstraint(unsigned Constraint) {
408407
assert((isMemKind() || isFuncKind()) &&
409408
"Flag is not a memory or function constraint!");
409+
assert(Constraint <= Constraints_Max && "Unknown constraint ID");
410410
assert(getData() == 0 && "Mem constraint already set");
411-
setData(static_cast<uint32_t>(C));
411+
setData(Constraint);
412412
}
413413
/// clearMemConstraint - Similar to setMemConstraint(0), but without the
414414
/// assertion checking that the constraint has not been set previously.
@@ -443,63 +443,63 @@ class InlineAsm final : public Value {
443443
return Result;
444444
}
445445

446-
static StringRef getMemConstraintName(ConstraintCode C) {
447-
switch (C) {
448-
case ConstraintCode::es:
446+
static StringRef getMemConstraintName(unsigned Constraint) {
447+
switch (Constraint) {
448+
case InlineAsm::Constraint_es:
449449
return "es";
450-
case ConstraintCode::i:
450+
case InlineAsm::Constraint_i:
451451
return "i";
452-
case ConstraintCode::k:
452+
case InlineAsm::Constraint_k:
453453
return "k";
454-
case ConstraintCode::m:
454+
case InlineAsm::Constraint_m:
455455
return "m";
456-
case ConstraintCode::o:
456+
case InlineAsm::Constraint_o:
457457
return "o";
458-
case ConstraintCode::v:
458+
case InlineAsm::Constraint_v:
459459
return "v";
460-
case ConstraintCode::A:
460+
case InlineAsm::Constraint_A:
461461
return "A";
462-
case ConstraintCode::Q:
462+
case InlineAsm::Constraint_Q:
463463
return "Q";
464-
case ConstraintCode::R:
464+
case InlineAsm::Constraint_R:
465465
return "R";
466-
case ConstraintCode::S:
466+
case InlineAsm::Constraint_S:
467467
return "S";
468-
case ConstraintCode::T:
468+
case InlineAsm::Constraint_T:
469469
return "T";
470-
case ConstraintCode::Um:
470+
case InlineAsm::Constraint_Um:
471471
return "Um";
472-
case ConstraintCode::Un:
472+
case InlineAsm::Constraint_Un:
473473
return "Un";
474-
case ConstraintCode::Uq:
474+
case InlineAsm::Constraint_Uq:
475475
return "Uq";
476-
case ConstraintCode::Us:
476+
case InlineAsm::Constraint_Us:
477477
return "Us";
478-
case ConstraintCode::Ut:
478+
case InlineAsm::Constraint_Ut:
479479
return "Ut";
480-
case ConstraintCode::Uv:
480+
case InlineAsm::Constraint_Uv:
481481
return "Uv";
482-
case ConstraintCode::Uy:
482+
case InlineAsm::Constraint_Uy:
483483
return "Uy";
484-
case ConstraintCode::X:
484+
case InlineAsm::Constraint_X:
485485
return "X";
486-
case ConstraintCode::Z:
486+
case InlineAsm::Constraint_Z:
487487
return "Z";
488-
case ConstraintCode::ZB:
488+
case InlineAsm::Constraint_ZB:
489489
return "ZB";
490-
case ConstraintCode::ZC:
490+
case InlineAsm::Constraint_ZC:
491491
return "ZC";
492-
case ConstraintCode::Zy:
492+
case InlineAsm::Constraint_Zy:
493493
return "Zy";
494-
case ConstraintCode::p:
494+
case InlineAsm::Constraint_p:
495495
return "p";
496-
case ConstraintCode::ZQ:
496+
case InlineAsm::Constraint_ZQ:
497497
return "ZQ";
498-
case ConstraintCode::ZR:
498+
case InlineAsm::Constraint_ZR:
499499
return "ZR";
500-
case ConstraintCode::ZS:
500+
case InlineAsm::Constraint_ZS:
501501
return "ZS";
502-
case ConstraintCode::ZT:
502+
case InlineAsm::Constraint_ZT:
503503
return "ZT";
504504
default:
505505
llvm_unreachable("Unknown memory constraint");

‎llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp

+3-3
Original file line numberDiff line numberDiff line change
@@ -373,9 +373,9 @@ bool InlineAsmLowering::lowerInlineAsm(
373373
switch (OpInfo.Type) {
374374
case InlineAsm::isOutput:
375375
if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
376-
const InlineAsm::ConstraintCode ConstraintID =
376+
unsigned ConstraintID =
377377
TLI->getInlineAsmMemConstraint(OpInfo.ConstraintCode);
378-
assert(ConstraintID != InlineAsm::ConstraintCode::Unknown &&
378+
assert(ConstraintID != InlineAsm::Constraint_Unknown &&
379379
"Failed to convert memory constraint code to constraint id.");
380380

381381
// Add information to the INLINEASM instruction to know about this
@@ -517,7 +517,7 @@ bool InlineAsmLowering::lowerInlineAsm(
517517

518518
assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
519519

520-
const InlineAsm::ConstraintCode ConstraintID =
520+
unsigned ConstraintID =
521521
TLI->getInlineAsmMemConstraint(OpInfo.ConstraintCode);
522522
InlineAsm::Flag OpFlags(InlineAsm::Kind::Mem, 1);
523523
OpFlags.setMemConstraint(ConstraintID);

‎llvm/lib/CodeGen/MachineInstr.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -1778,7 +1778,7 @@ void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
17781778
}
17791779

17801780
if (F.isMemKind()) {
1781-
const InlineAsm::ConstraintCode MCID = F.getMemoryConstraintID();
1781+
const unsigned MCID = F.getMemoryConstraintID();
17821782
OS << ":" << InlineAsm::getMemConstraintName(MCID);
17831783
}
17841784

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

+6-6
Original file line numberDiff line numberDiff line change
@@ -9281,9 +9281,9 @@ void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call,
92819281
switch (OpInfo.Type) {
92829282
case InlineAsm::isOutput:
92839283
if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
9284-
const InlineAsm::ConstraintCode ConstraintID =
9284+
unsigned ConstraintID =
92859285
TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
9286-
assert(ConstraintID != InlineAsm::ConstraintCode::Unknown &&
9286+
assert(ConstraintID != InlineAsm::Constraint_Unknown &&
92879287
"Failed to convert memory constraint code to constraint id.");
92889288

92899289
// Add information to the INLINEASM node to know about this output.
@@ -9413,9 +9413,9 @@ void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call,
94139413
TLI.getPointerTy(DAG.getDataLayout()) &&
94149414
"Memory operands expect pointer values");
94159415

9416-
const InlineAsm::ConstraintCode ConstraintID =
9416+
unsigned ConstraintID =
94179417
TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
9418-
assert(ConstraintID != InlineAsm::ConstraintCode::Unknown &&
9418+
assert(ConstraintID != InlineAsm::Constraint_Unknown &&
94199419
"Failed to convert memory constraint code to constraint id.");
94209420

94219421
// Add information to the INLINEASM node to know about this input.
@@ -9429,9 +9429,9 @@ void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call,
94299429
}
94309430

94319431
if (OpInfo.ConstraintType == TargetLowering::C_Address) {
9432-
const InlineAsm::ConstraintCode ConstraintID =
9432+
unsigned ConstraintID =
94339433
TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
9434-
assert(ConstraintID != InlineAsm::ConstraintCode::Unknown &&
9434+
assert(ConstraintID != InlineAsm::Constraint_Unknown &&
94359435
"Failed to convert memory constraint code to constraint id.");
94369436

94379437
InlineAsm::Flag ResOpType(InlineAsm::Kind::Mem, 1);

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

+1-2
Original file line numberDiff line numberDiff line change
@@ -2101,8 +2101,7 @@ void SelectionDAGISel::SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops,
21012101

21022102
// Otherwise, this is a memory operand. Ask the target to select it.
21032103
std::vector<SDValue> SelOps;
2104-
const InlineAsm::ConstraintCode ConstraintID =
2105-
Flags.getMemoryConstraintID();
2104+
unsigned ConstraintID = Flags.getMemoryConstraintID();
21062105
if (SelectInlineAsmMemoryOperand(InOps[i+1], ConstraintID, SelOps))
21072106
report_fatal_error("Could not match memory address. Inline asm"
21082107
" failure!");

‎llvm/lib/CodeGen/TargetInstrInfo.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -1622,7 +1622,7 @@ std::string TargetInstrInfo::createMIROperandComment(
16221622
}
16231623

16241624
if (F.isMemKind()) {
1625-
InlineAsm::ConstraintCode MCID = F.getMemoryConstraintID();
1625+
const unsigned MCID = F.getMemoryConstraintID();
16261626
OS << ":" << InlineAsm::getMemConstraintName(MCID);
16271627
}
16281628

‎llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp

+5-6
Original file line numberDiff line numberDiff line change
@@ -62,7 +62,7 @@ class AArch64DAGToDAGISel : public SelectionDAGISel {
6262
/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
6363
/// inline asm expressions.
6464
bool SelectInlineAsmMemoryOperand(const SDValue &Op,
65-
InlineAsm::ConstraintCode ConstraintID,
65+
unsigned ConstraintID,
6666
std::vector<SDValue> &OutOps) override;
6767

6868
template <signed Low, signed High, signed Scale>
@@ -533,14 +533,13 @@ static bool isIntImmediateEq(SDValue N, const uint64_t ImmExpected) {
533533
#endif
534534

535535
bool AArch64DAGToDAGISel::SelectInlineAsmMemoryOperand(
536-
const SDValue &Op, const InlineAsm::ConstraintCode ConstraintID,
537-
std::vector<SDValue> &OutOps) {
536+
const SDValue &Op, unsigned ConstraintID, std::vector<SDValue> &OutOps) {
538537
switch(ConstraintID) {
539538
default:
540539
llvm_unreachable("Unexpected asm memory constraint");
541-
case InlineAsm::ConstraintCode::m:
542-
case InlineAsm::ConstraintCode::o:
543-
case InlineAsm::ConstraintCode::Q:
540+
case InlineAsm::Constraint_m:
541+
case InlineAsm::Constraint_o:
542+
case InlineAsm::Constraint_Q:
544543
// We need to make sure that this one operand does not end up in XZR, thus
545544
// require the address to be in a PointerRegClass register.
546545
const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();

‎llvm/lib/Target/AArch64/AArch64ISelLowering.h

+2-3
Original file line numberDiff line numberDiff line change
@@ -1169,10 +1169,9 @@ class AArch64TargetLowering : public TargetLowering {
11691169
std::vector<SDValue> &Ops,
11701170
SelectionDAG &DAG) const override;
11711171

1172-
InlineAsm::ConstraintCode
1173-
getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
1172+
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
11741173
if (ConstraintCode == "Q")
1175-
return InlineAsm::ConstraintCode::Q;
1174+
return InlineAsm::Constraint_Q;
11761175
// FIXME: clang has code for 'Ump', 'Utf', 'Usa', and 'Ush' but these are
11771176
// followed by llvm_unreachable so we'll leave them unimplemented in
11781177
// the backend for now.

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