@@ -660,17 +660,17 @@ static void printMask(raw_ostream &OS, LaneBitmask Val) {
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// Try to combine Idx's compose map into Vec if it is compatible.
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// Return false if it's not possible.
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static bool combine (const CodeGenSubRegIndex *Idx,
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- SmallVectorImpl<CodeGenSubRegIndex *> &Vec) {
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+ SmallVectorImpl<const CodeGenSubRegIndex *> &Vec) {
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const CodeGenSubRegIndex::CompMap &Map = Idx->getComposites ();
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for (const auto &I : Map) {
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- CodeGenSubRegIndex *&Entry = Vec[I.first ->EnumValue - 1 ];
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+ const CodeGenSubRegIndex *&Entry = Vec[I.first ->EnumValue - 1 ];
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if (Entry && Entry != I.second )
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return false ;
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}
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// All entries are compatible. Make it so.
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for (const auto &I : Map) {
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- auto *&Entry = Vec[I.first ->EnumValue - 1 ];
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+ const CodeGenSubRegIndex *&Entry = Vec[I.first ->EnumValue - 1 ];
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assert ((!Entry || Entry == I.second ) && " Expected EnumValue to be unique" );
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Entry = I.second ;
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}
@@ -692,7 +692,7 @@ void RegisterInfoEmitter::emitComposeSubRegIndices(raw_ostream &OS,
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// Map each Sub-register index to a compatible table row.
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SmallVector<unsigned , 4 > RowMap;
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- SmallVector<SmallVector<CodeGenSubRegIndex *, 4 >, 4 > Rows;
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+ SmallVector<SmallVector<const CodeGenSubRegIndex *, 4 >, 4 > Rows;
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auto SubRegIndicesSize =
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std::distance (SubRegIndices.begin (), SubRegIndices.end ());
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