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[RISCV] Keep same SEW/LMUL ratio if possible in forward transfer (llvm#69788)
For instructions like vmv.s.x and friends where we don't care about LMUL or the SEW/LMUL ratio, we can change the LMUL in its state so that it has the same SEW/LMUL ratio as the previous state. This allows us to avoid more VL toggles later down the line (i.e. use vsetvli zero, zero, which requires that the SEW/LMUL ratio must be the same) This is an alternative approach to the idea in llvm#69259, but note that they don't catch exactly the same test cases.
1 parent b23426e commit c8e1fbc

21 files changed

+305
-294
lines changed

‎llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp

+4-3
Original file line numberDiff line numberDiff line change
@@ -212,9 +212,10 @@ getEEWAndEMULForUnitStrideLoadStore(unsigned Opcode, RISCVII::VLMUL LMUL,
212212
llvm_unreachable("Opcode is not a vector unit stride load nor store");
213213
}
214214

215-
uint8_t EMUL =
216-
static_cast<uint8_t>(RISCVVType::getSameRatioLMUL(SEW, LMUL, EEW));
217-
return std::make_pair(EEW, EMUL);
215+
auto EMUL = RISCVVType::getSameRatioLMUL(SEW, LMUL, EEW);
216+
if (!EEW)
217+
llvm_unreachable("Invalid SEW or LMUL for new ratio");
218+
return std::make_pair(EEW, *EMUL);
218219
}
219220

220221
unsigned RISCVInstrumentManager::getSchedClassID(

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp

+4-2
Original file line numberDiff line numberDiff line change
@@ -206,12 +206,14 @@ unsigned RISCVVType::getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul) {
206206
return (SEW * 8) / LMul;
207207
}
208208

209-
RISCVII::VLMUL RISCVVType::getSameRatioLMUL(unsigned SEW, RISCVII::VLMUL VLMUL,
210-
unsigned EEW) {
209+
std::optional<RISCVII::VLMUL>
210+
RISCVVType::getSameRatioLMUL(unsigned SEW, RISCVII::VLMUL VLMUL, unsigned EEW) {
211211
unsigned Ratio = RISCVVType::getSEWLMULRatio(SEW, VLMUL);
212212
unsigned EMULFixedPoint = (EEW * 8) / Ratio;
213213
bool Fractional = EMULFixedPoint < 8;
214214
unsigned EMUL = Fractional ? 8 / EMULFixedPoint : EMULFixedPoint / 8;
215+
if (!isValidLMUL(EMUL, Fractional))
216+
return std::nullopt;
215217
return RISCVVType::encodeLMUL(EMUL, Fractional);
216218
}
217219

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

+2-2
Original file line numberDiff line numberDiff line change
@@ -535,8 +535,8 @@ void printVType(unsigned VType, raw_ostream &OS);
535535

536536
unsigned getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul);
537537

538-
RISCVII::VLMUL getSameRatioLMUL(unsigned SEW, RISCVII::VLMUL VLMUL,
539-
unsigned EEW);
538+
std::optional<RISCVII::VLMUL>
539+
getSameRatioLMUL(unsigned SEW, RISCVII::VLMUL VLMUL, unsigned EEW);
540540
} // namespace RISCVVType
541541

542542
namespace RISCVRVC {

‎llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

+13
Original file line numberDiff line numberDiff line change
@@ -539,6 +539,8 @@ class VSETVLIInfo {
539539
MaskAgnostic = MA;
540540
}
541541

542+
void setVLMul(RISCVII::VLMUL VLMul) { this->VLMul = VLMul; }
543+
542544
unsigned encodeVTYPE() const {
543545
assert(isValid() && !isUnknown() && !SEWLMULRatioOnly &&
544546
"Can't encode VTYPE for uninitialized or unknown");
@@ -1038,6 +1040,17 @@ void RISCVInsertVSETVLI::transferBefore(VSETVLIInfo &Info,
10381040
if (!RISCVII::hasVLOp(TSFlags))
10391041
return;
10401042

1043+
// If we don't use LMUL or the SEW/LMUL ratio, then adjust LMUL so that we
1044+
// maintain the SEW/LMUL ratio. This allows us to eliminate VL toggles in more
1045+
// places.
1046+
DemandedFields Demanded = getDemanded(MI, MRI, ST);
1047+
if (!Demanded.LMUL && !Demanded.SEWLMULRatio && Info.isValid() &&
1048+
PrevInfo.isValid() && !Info.isUnknown() && !PrevInfo.isUnknown()) {
1049+
if (auto NewVLMul = RISCVVType::getSameRatioLMUL(
1050+
PrevInfo.getSEW(), PrevInfo.getVLMUL(), Info.getSEW()))
1051+
Info.setVLMul(*NewVLMul);
1052+
}
1053+
10411054
// For vmv.s.x and vfmv.s.f, there are only two behaviors, VL = 0 and
10421055
// VL > 0. We can discard the user requested AVL and just use the last
10431056
// one if we can prove it equally zero. This removes a vsetvli entirely

‎llvm/test/CodeGen/RISCV/double_reduct.ll

+1-1
Original file line numberDiff line numberDiff line change
@@ -90,7 +90,7 @@ define i16 @add_ext_i16(<16 x i8> %a, <16 x i8> %b) {
9090
; CHECK: # %bb.0:
9191
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
9292
; CHECK-NEXT: vwaddu.vv v10, v8, v9
93-
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
93+
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
9494
; CHECK-NEXT: vmv.s.x v8, zero
9595
; CHECK-NEXT: vredsum.vs v8, v10, v8
9696
; CHECK-NEXT: vmv.x.s a0, v8

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-deinterleave-load.ll

+2-2
Original file line numberDiff line numberDiff line change
@@ -22,9 +22,9 @@ define {<16 x i1>, <16 x i1>} @vector_deinterleave_load_v16i1_v32i1(ptr %p) {
2222
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
2323
; CHECK-NEXT: vadd.vi v12, v11, -16
2424
; CHECK-NEXT: li a0, -256
25-
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
25+
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
2626
; CHECK-NEXT: vmv.s.x v0, a0
27-
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
27+
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu
2828
; CHECK-NEXT: vrgather.vv v9, v8, v12, v0.t
2929
; CHECK-NEXT: vmsne.vi v9, v9, 0
3030
; CHECK-NEXT: vadd.vi v12, v11, 1

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll

+2-2
Original file line numberDiff line numberDiff line change
@@ -550,9 +550,9 @@ define void @insertelt_c6_v8i64_0_add(ptr %x, ptr %y) {
550550
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
551551
; CHECK-NEXT: vle64.v v8, (a0)
552552
; CHECK-NEXT: li a2, 6
553-
; CHECK-NEXT: vsetivli zero, 8, e64, m1, tu, ma
553+
; CHECK-NEXT: vsetvli zero, zero, e64, m4, tu, ma
554554
; CHECK-NEXT: vmv.s.x v8, a2
555-
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
555+
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
556556
; CHECK-NEXT: vle64.v v12, (a1)
557557
; CHECK-NEXT: vadd.vv v8, v8, v12
558558
; CHECK-NEXT: vse64.v v8, (a0)

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll

+2-2
Original file line numberDiff line numberDiff line change
@@ -567,9 +567,9 @@ define void @buildvec_seq_v9i8(ptr %x) {
567567
; CHECK-NEXT: vmv.v.i v8, 3
568568
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
569569
; CHECK-NEXT: li a1, 146
570-
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
570+
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
571571
; CHECK-NEXT: vmv.s.x v0, a1
572-
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
572+
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
573573
; CHECK-NEXT: vmerge.vim v8, v8, 2, v0
574574
; CHECK-NEXT: vsetivli zero, 9, e8, m1, ta, ma
575575
; CHECK-NEXT: vse8.v v8, (a0)

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll

+53-55
Original file line numberDiff line numberDiff line change
@@ -1101,21 +1101,20 @@ define void @urem_v2i64(ptr %x, ptr %y) {
11011101
define void @mulhu_v16i8(ptr %x) {
11021102
; CHECK-LABEL: mulhu_v16i8:
11031103
; CHECK: # %bb.0:
1104-
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
1104+
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
11051105
; CHECK-NEXT: vle8.v v8, (a0)
11061106
; CHECK-NEXT: lui a1, 3
11071107
; CHECK-NEXT: addi a1, a1, -2044
1108-
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
11091108
; CHECK-NEXT: vmv.s.x v0, a1
1110-
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
1109+
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
11111110
; CHECK-NEXT: vmv.v.i v9, 0
11121111
; CHECK-NEXT: li a1, -128
11131112
; CHECK-NEXT: vmerge.vxm v10, v9, a1, v0
11141113
; CHECK-NEXT: lui a1, 1
11151114
; CHECK-NEXT: addi a2, a1, 32
1116-
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
1115+
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
11171116
; CHECK-NEXT: vmv.s.x v0, a2
1118-
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
1117+
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
11191118
; CHECK-NEXT: lui a2, %hi(.LCPI65_0)
11201119
; CHECK-NEXT: addi a2, a2, %lo(.LCPI65_0)
11211120
; CHECK-NEXT: vle8.v v11, (a2)
@@ -1126,21 +1125,21 @@ define void @mulhu_v16i8(ptr %x) {
11261125
; CHECK-NEXT: vmulhu.vv v8, v8, v10
11271126
; CHECK-NEXT: vadd.vv v8, v8, v9
11281127
; CHECK-NEXT: li a2, 513
1129-
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
1128+
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
11301129
; CHECK-NEXT: vmv.s.x v0, a2
1131-
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
1130+
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
11321131
; CHECK-NEXT: vmv.v.i v9, 4
11331132
; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
11341133
; CHECK-NEXT: addi a1, a1, 78
1135-
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
1134+
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
11361135
; CHECK-NEXT: vmv.s.x v0, a1
1137-
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
1136+
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
11381137
; CHECK-NEXT: vmerge.vim v9, v9, 3, v0
11391138
; CHECK-NEXT: lui a1, 8
11401139
; CHECK-NEXT: addi a1, a1, 304
1141-
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
1140+
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
11421141
; CHECK-NEXT: vmv.s.x v0, a1
1143-
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
1142+
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
11441143
; CHECK-NEXT: vmerge.vim v9, v9, 2, v0
11451144
; CHECK-NEXT: vsrl.vv v8, v8, v9
11461145
; CHECK-NEXT: vse8.v v8, (a0)
@@ -1204,9 +1203,9 @@ define void @mulhu_v6i16(ptr %x) {
12041203
; CHECK-NEXT: vdivu.vv v9, v10, v9
12051204
; CHECK-NEXT: lui a1, 45217
12061205
; CHECK-NEXT: addi a1, a1, -1785
1207-
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
1206+
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
12081207
; CHECK-NEXT: vmv.s.x v10, a1
1209-
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
1208+
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
12101209
; CHECK-NEXT: vsext.vf2 v11, v10
12111210
; CHECK-NEXT: vdivu.vv v8, v8, v11
12121211
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
@@ -1309,10 +1308,10 @@ define void @mulhs_v16i8(ptr %x) {
13091308
; CHECK-NEXT: vmv.v.x v9, a1
13101309
; CHECK-NEXT: lui a1, 5
13111310
; CHECK-NEXT: addi a1, a1, -1452
1312-
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
1311+
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
13131312
; CHECK-NEXT: vmv.s.x v0, a1
13141313
; CHECK-NEXT: li a1, 57
1315-
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
1314+
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
13161315
; CHECK-NEXT: vmerge.vxm v9, v9, a1, v0
13171316
; CHECK-NEXT: vmulhu.vv v8, v8, v9
13181317
; CHECK-NEXT: vmv.v.i v9, 7
@@ -1367,9 +1366,9 @@ define void @mulhs_v6i16(ptr %x) {
13671366
; CHECK-NEXT: vdiv.vv v9, v9, v10
13681367
; CHECK-NEXT: lui a1, 1020016
13691368
; CHECK-NEXT: addi a1, a1, 2041
1370-
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
1369+
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
13711370
; CHECK-NEXT: vmv.s.x v10, a1
1372-
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
1371+
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
13731372
; CHECK-NEXT: vsext.vf2 v11, v10
13741373
; CHECK-NEXT: vdiv.vv v8, v8, v11
13751374
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
@@ -4872,45 +4871,45 @@ define void @mulhu_v32i8(ptr %x) {
48724871
; LMULMAX2-NEXT: vsetvli zero, a1, e8, m2, ta, ma
48734872
; LMULMAX2-NEXT: vle8.v v8, (a0)
48744873
; LMULMAX2-NEXT: vmv.v.i v10, 0
4875-
; LMULMAX2-NEXT: lui a2, 163907
4876-
; LMULMAX2-NEXT: addi a2, a2, -2044
4877-
; LMULMAX2-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
4878-
; LMULMAX2-NEXT: vmv.s.x v0, a2
4879-
; LMULMAX2-NEXT: li a2, -128
4880-
; LMULMAX2-NEXT: vsetvli zero, a1, e8, m2, ta, ma
4881-
; LMULMAX2-NEXT: vmerge.vxm v12, v10, a2, v0
4882-
; LMULMAX2-NEXT: lui a2, 66049
4883-
; LMULMAX2-NEXT: addi a2, a2, 32
4884-
; LMULMAX2-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
4885-
; LMULMAX2-NEXT: vmv.s.x v0, a2
4886-
; LMULMAX2-NEXT: vsetvli zero, a1, e8, m2, ta, ma
4887-
; LMULMAX2-NEXT: lui a2, %hi(.LCPI181_0)
4888-
; LMULMAX2-NEXT: addi a2, a2, %lo(.LCPI181_0)
4889-
; LMULMAX2-NEXT: vle8.v v14, (a2)
4874+
; LMULMAX2-NEXT: lui a1, 163907
4875+
; LMULMAX2-NEXT: addi a1, a1, -2044
4876+
; LMULMAX2-NEXT: vsetvli zero, zero, e32, m8, ta, ma
4877+
; LMULMAX2-NEXT: vmv.s.x v0, a1
4878+
; LMULMAX2-NEXT: li a1, -128
4879+
; LMULMAX2-NEXT: vsetvli zero, zero, e8, m2, ta, ma
4880+
; LMULMAX2-NEXT: vmerge.vxm v12, v10, a1, v0
4881+
; LMULMAX2-NEXT: lui a1, 66049
4882+
; LMULMAX2-NEXT: addi a1, a1, 32
4883+
; LMULMAX2-NEXT: vsetvli zero, zero, e32, m8, ta, ma
4884+
; LMULMAX2-NEXT: vmv.s.x v0, a1
4885+
; LMULMAX2-NEXT: vsetvli zero, zero, e8, m2, ta, ma
4886+
; LMULMAX2-NEXT: lui a1, %hi(.LCPI181_0)
4887+
; LMULMAX2-NEXT: addi a1, a1, %lo(.LCPI181_0)
4888+
; LMULMAX2-NEXT: vle8.v v14, (a1)
48904889
; LMULMAX2-NEXT: vmerge.vim v10, v10, 1, v0
48914890
; LMULMAX2-NEXT: vsrl.vv v10, v8, v10
48924891
; LMULMAX2-NEXT: vmulhu.vv v10, v10, v14
48934892
; LMULMAX2-NEXT: vsub.vv v8, v8, v10
48944893
; LMULMAX2-NEXT: vmulhu.vv v8, v8, v12
48954894
; LMULMAX2-NEXT: vadd.vv v8, v8, v10
48964895
; LMULMAX2-NEXT: vmv.v.i v10, 4
4897-
; LMULMAX2-NEXT: lui a2, 8208
4898-
; LMULMAX2-NEXT: addi a2, a2, 513
4899-
; LMULMAX2-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
4900-
; LMULMAX2-NEXT: vmv.s.x v0, a2
4901-
; LMULMAX2-NEXT: vsetvli zero, a1, e8, m2, ta, ma
4896+
; LMULMAX2-NEXT: lui a1, 8208
4897+
; LMULMAX2-NEXT: addi a1, a1, 513
4898+
; LMULMAX2-NEXT: vsetvli zero, zero, e32, m8, ta, ma
4899+
; LMULMAX2-NEXT: vmv.s.x v0, a1
4900+
; LMULMAX2-NEXT: vsetvli zero, zero, e8, m2, ta, ma
49024901
; LMULMAX2-NEXT: vmerge.vim v10, v10, 1, v0
4903-
; LMULMAX2-NEXT: lui a2, 66785
4904-
; LMULMAX2-NEXT: addi a2, a2, 78
4905-
; LMULMAX2-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
4906-
; LMULMAX2-NEXT: vmv.s.x v0, a2
4907-
; LMULMAX2-NEXT: vsetvli zero, a1, e8, m2, ta, ma
4902+
; LMULMAX2-NEXT: lui a1, 66785
4903+
; LMULMAX2-NEXT: addi a1, a1, 78
4904+
; LMULMAX2-NEXT: vsetvli zero, zero, e32, m8, ta, ma
4905+
; LMULMAX2-NEXT: vmv.s.x v0, a1
4906+
; LMULMAX2-NEXT: vsetvli zero, zero, e8, m2, ta, ma
49084907
; LMULMAX2-NEXT: vmerge.vim v10, v10, 3, v0
4909-
; LMULMAX2-NEXT: lui a2, 529160
4910-
; LMULMAX2-NEXT: addi a2, a2, 304
4911-
; LMULMAX2-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
4912-
; LMULMAX2-NEXT: vmv.s.x v0, a2
4913-
; LMULMAX2-NEXT: vsetvli zero, a1, e8, m2, ta, ma
4908+
; LMULMAX2-NEXT: lui a1, 529160
4909+
; LMULMAX2-NEXT: addi a1, a1, 304
4910+
; LMULMAX2-NEXT: vsetvli zero, zero, e32, m8, ta, ma
4911+
; LMULMAX2-NEXT: vmv.s.x v0, a1
4912+
; LMULMAX2-NEXT: vsetvli zero, zero, e8, m2, ta, ma
49144913
; LMULMAX2-NEXT: vmerge.vim v10, v10, 2, v0
49154914
; LMULMAX2-NEXT: vsrl.vv v8, v8, v10
49164915
; LMULMAX2-NEXT: vse8.v v8, (a0)
@@ -5250,11 +5249,11 @@ define void @mulhs_v32i8(ptr %x) {
52505249
; LMULMAX2-NEXT: vsetvli zero, a1, e8, m2, ta, ma
52515250
; LMULMAX2-NEXT: vle8.v v8, (a0)
52525251
; LMULMAX2-NEXT: vmv.v.i v10, 7
5253-
; LMULMAX2-NEXT: lui a2, 304453
5254-
; LMULMAX2-NEXT: addi a2, a2, -1452
5255-
; LMULMAX2-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
5256-
; LMULMAX2-NEXT: vmv.s.x v0, a2
5257-
; LMULMAX2-NEXT: vsetvli zero, a1, e8, m2, ta, ma
5252+
; LMULMAX2-NEXT: lui a1, 304453
5253+
; LMULMAX2-NEXT: addi a1, a1, -1452
5254+
; LMULMAX2-NEXT: vsetvli zero, zero, e32, m8, ta, ma
5255+
; LMULMAX2-NEXT: vmv.s.x v0, a1
5256+
; LMULMAX2-NEXT: vsetvli zero, zero, e8, m2, ta, ma
52585257
; LMULMAX2-NEXT: vmerge.vim v10, v10, 1, v0
52595258
; LMULMAX2-NEXT: li a1, -123
52605259
; LMULMAX2-NEXT: vmv.v.x v12, a1
@@ -5267,15 +5266,14 @@ define void @mulhs_v32i8(ptr %x) {
52675266
;
52685267
; LMULMAX1-LABEL: mulhs_v32i8:
52695268
; LMULMAX1: # %bb.0:
5270-
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, ma
5269+
; LMULMAX1-NEXT: vsetivli zero, 16, e16, m2, ta, ma
52715270
; LMULMAX1-NEXT: vle8.v v8, (a0)
52725271
; LMULMAX1-NEXT: addi a1, a0, 16
52735272
; LMULMAX1-NEXT: vle8.v v9, (a1)
52745273
; LMULMAX1-NEXT: lui a2, 5
52755274
; LMULMAX1-NEXT: addi a2, a2, -1452
5276-
; LMULMAX1-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
52775275
; LMULMAX1-NEXT: vmv.s.x v0, a2
5278-
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, ma
5276+
; LMULMAX1-NEXT: vsetvli zero, zero, e8, m1, ta, ma
52795277
; LMULMAX1-NEXT: vmv.v.i v10, -9
52805278
; LMULMAX1-NEXT: vmerge.vim v10, v10, 9, v0
52815279
; LMULMAX1-NEXT: vdivu.vv v9, v9, v10

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