boards: intel: Updated TSC frequency values

Updated TSC frequency values of intel boards.

Signed-off-by: Anisetti Avinash Krishna <[email protected]>

Author: akanisetti

boards/intel/adl/Kconfig.defconfig

@@ -7,10 +7,10 @@ config BUILD_OUTPUT_STRIPPED
 config MP_MAX_NUM_CPUS
 	default 2
 
-# TSC on this board is 1.9 GHz, HPET and APIC are 19.2 MHz
+# TSC on this board is 1.5 GHz, HPET and APIC are 19.2 MHz
 config SYS_CLOCK_HW_CYCLES_PER_SEC
-	default 1900000000 if APIC_TSC_DEADLINE_TIMER
-	default 1900000000 if APIC_TIMER_TSC
+	default 1500000000 if APIC_TSC_DEADLINE_TIMER
+	default 1500000000 if APIC_TIMER_TSC
 	default 19200000
 
 if APIC_TIMER

boards/intel/rpl/Kconfig.defconfig

@@ -8,12 +8,26 @@ config BUILD_OUTPUT_STRIPPED
 config MP_MAX_NUM_CPUS
 	default 2
 
-# TSC on this board is 1.9 GHz, HPET and APIC are 19.2 MHz
+if BOARD_INTEL_RPL_S_CRB
+
+# TSC on this board is 2.4 GHz for RPL-S, HPET and APIC are 19.2 MHz
 config SYS_CLOCK_HW_CYCLES_PER_SEC
-	default 1900000000 if APIC_TSC_DEADLINE_TIMER
-	default 1900000000 if APIC_TIMER_TSC
+	default 2400000000 if APIC_TSC_DEADLINE_TIMER
+	default 2400000000 if APIC_TIMER_TSC
 	default 19200000
 
+endif #BOARD_INTEL_RPL_S_CRB
+
+if BOARD_INTEL_RPL_P_CRB
+
+# TSC on this board is 1.8 GHz for RPL-P, HPET and APIC are 19.2 MHz
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 1800000000 if APIC_TSC_DEADLINE_TIMER
+	default 1800000000 if APIC_TIMER_TSC
+	default 19200000
+
+endif #BOARD_INTEL_RPL_P_CRB
+
 if APIC_TIMER
 config APIC_TIMER_IRQ
 	default 24