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Unchanged file from zephyrproject-rtos#27058
rebased on current master

find . -iname *.h -o -iname *.cpp -o -iname *.c | xargs clang-format-12 -style=file -i

Author: chrta

arch/arc/core/arc_connect.c

@@ -16,7 +16,6 @@
 #include <soc.h>
 #include <init.h>
 
-
 #ifndef IRQ_ICI
 #define IRQ_ICI 19
 #endif
@@ -119,15 +118,14 @@ static int arc_smp_init(const struct device *dev)
 	bcr.val = z_arc_v2_aux_reg_read(_ARC_V2_CONNECT_BCR);
 
 	if (bcr.ipi) {
-	/* register ici interrupt, just need master core to register once */
+		/* register ici interrupt, just need master core to register once */
 		z_arc_connect_ici_clear();
-		IRQ_CONNECT(IRQ_ICI, ARCV2_ICI_IRQ_PRIORITY,
-		    sched_ipi_handler, NULL, 0);
+		IRQ_CONNECT(IRQ_ICI, ARCV2_ICI_IRQ_PRIORITY, sched_ipi_handler,
+			    NULL, 0);
 
 		irq_enable(IRQ_ICI);
 	} else {
-		__ASSERT(0,
-			"ARC connect has no inter-core interrupt\n");
+		__ASSERT(0, "ARC connect has no inter-core interrupt\n");
 		return -ENODEV;
 	}
 
@@ -139,8 +137,7 @@ static int arc_smp_init(const struct device *dev)
 		z_arc_connect_gfrc_core_set((1 << CONFIG_MP_NUM_CPUS) - 1);
 		z_arc_connect_gfrc_clear();
 	} else {
-		__ASSERT(0,
-			"ARC connect has no global free running counter\n");
+		__ASSERT(0, "ARC connect has no global free running counter\n");
 		return -ENODEV;
 	}
 

arch/arc/core/arc_smp.c

@@ -35,17 +35,16 @@
 #define DCACHE_LINE_SIZE CONFIG_CACHE_LINE_SIZE
 #endif
 
-#define DC_CTRL_DC_ENABLE            0x0  /* enable d-cache */
-#define DC_CTRL_DC_DISABLE           0x1  /* disable d-cache */
-#define DC_CTRL_INVALID_ONLY         0x0  /* invalid d-cache only */
-#define DC_CTRL_INVALID_FLUSH        0x40 /* invalid and flush d-cache */
-#define DC_CTRL_ENABLE_FLUSH_LOCKED  0x80 /* locked d-cache can be flushed */
-#define DC_CTRL_DISABLE_FLUSH_LOCKED 0x0  /* locked d-cache cannot be flushed */
-#define DC_CTRL_FLUSH_STATUS         0x100/* flush status */
-#define DC_CTRL_DIRECT_ACCESS        0x0  /* direct access mode  */
-#define DC_CTRL_INDIRECT_ACCESS      0x20 /* indirect access mode */
-#define DC_CTRL_OP_SUCCEEDED         0x4  /* d-cache operation succeeded */
-
+#define DC_CTRL_DC_ENABLE 0x0 /* enable d-cache */
+#define DC_CTRL_DC_DISABLE 0x1 /* disable d-cache */
+#define DC_CTRL_INVALID_ONLY 0x0 /* invalid d-cache only */
+#define DC_CTRL_INVALID_FLUSH 0x40 /* invalid and flush d-cache */
+#define DC_CTRL_ENABLE_FLUSH_LOCKED 0x80 /* locked d-cache can be flushed */
+#define DC_CTRL_DISABLE_FLUSH_LOCKED 0x0 /* locked d-cache cannot be flushed */
+#define DC_CTRL_FLUSH_STATUS 0x100 /* flush status */
+#define DC_CTRL_DIRECT_ACCESS 0x0 /* direct access mode  */
+#define DC_CTRL_INDIRECT_ACCESS 0x20 /* indirect access mode */
+#define DC_CTRL_OP_SUCCEEDED 0x4 /* d-cache operation succeeded */
 
 static bool dcache_available(void)
 {
@@ -99,7 +98,6 @@ void arch_dcache_flush(void *start_addr_ptr, size_t size)
 	} while (start_addr < end_addr);
 
 	arch_irq_unlock(key); /* --exit critical section-- */
-
 }
 
 void arch_dcache_invd(void *start_addr_ptr, size_t size)
@@ -133,10 +131,10 @@ static void init_dcache_line_size(void)
 	uint32_t val;
 
 	val = z_arc_v2_aux_reg_read(_ARC_V2_D_CACHE_BUILD);
-	__ASSERT((val&0xff) != 0U, "d-cache is not present");
-	val = ((val>>16) & 0xf) + 1;
+	__ASSERT((val & 0xff) != 0U, "d-cache is not present");
+	val = ((val >> 16) & 0xf) + 1;
 	val *= 16U;
-	sys_cache_line_size = (size_t) val;
+	sys_cache_line_size = (size_t)val;
 }
 #endif
 

arch/arc/core/cache.c

@@ -24,17 +24,17 @@ LOG_MODULE_DECLARE(os);
 #ifdef CONFIG_ARC_EXCEPTION_DEBUG
 static void dump_arc_esf(const z_arch_esf_t *esf)
 {
-	LOG_ERR(" r0: 0x%08x  r1: 0x%08x  r2: 0x%08x  r3: 0x%08x",
-		esf->r0, esf->r1, esf->r2, esf->r3);
-	LOG_ERR(" r4: 0x%08x  r5: 0x%08x  r6: 0x%08x  r7: 0x%08x",
-		esf->r4, esf->r5, esf->r6, esf->r7);
-	LOG_ERR(" r8: 0x%08x  r9: 0x%08x r10: 0x%08x r11: 0x%08x",
-		esf->r8, esf->r9, esf->r10, esf->r11);
-	LOG_ERR("r12: 0x%08x r13: 0x%08x  pc: 0x%08x",
-		esf->r12, esf->r13, esf->pc);
+	LOG_ERR(" r0: 0x%08x  r1: 0x%08x  r2: 0x%08x  r3: 0x%08x", esf->r0,
+		esf->r1, esf->r2, esf->r3);
+	LOG_ERR(" r4: 0x%08x  r5: 0x%08x  r6: 0x%08x  r7: 0x%08x", esf->r4,
+		esf->r5, esf->r6, esf->r7);
+	LOG_ERR(" r8: 0x%08x  r9: 0x%08x r10: 0x%08x r11: 0x%08x", esf->r8,
+		esf->r9, esf->r10, esf->r11);
+	LOG_ERR("r12: 0x%08x r13: 0x%08x  pc: 0x%08x", esf->r12, esf->r13,
+		esf->pc);
 	LOG_ERR(" blink: 0x%08x status32: 0x%08x", esf->blink, esf->status32);
-	LOG_ERR("lp_end: 0x%08x lp_start: 0x%08x lp_count: 0x%08x",
-		esf->lp_end, esf->lp_start, esf->lp_count);
+	LOG_ERR("lp_end: 0x%08x lp_start: 0x%08x lp_count: 0x%08x", esf->lp_end,
+		esf->lp_start, esf->lp_count);
 }
 #endif
 

arch/arc/core/fatal.c

@@ -25,9 +25,8 @@ LOG_MODULE_DECLARE(os);
 #ifdef CONFIG_USERSPACE
 Z_EXC_DECLARE(z_arc_user_string_nlen);
 
-static const struct z_exc_handle exceptions[] = {
-	Z_EXC_HANDLE(z_arc_user_string_nlen)
-};
+static const struct z_exc_handle exceptions[] = { Z_EXC_HANDLE(
+	z_arc_user_string_nlen) };
 #endif
 
 #if defined(CONFIG_MPU_STACK_GUARD)
@@ -87,7 +86,7 @@ static bool z_check_thread_stack_fail(const uint32_t fault_addr, uint32_t sp)
 		guard_start = guard_end - Z_ARC_STACK_GUARD_SIZE;
 	}
 
-	 /* treat any MPU exceptions within the guard region as a stack
+	/* treat any MPU exceptions within the guard region as a stack
 	  * overflow if the stack pointer is at or below the end of the guard
 	  * region.
 	  */
@@ -267,7 +266,8 @@ static void dump_privilege_exception(uint32_t cause, uint32_t parameter)
 	}
 }
 
-static void dump_exception_info(uint32_t vector, uint32_t cause, uint32_t parameter)
+static void dump_exception_info(uint32_t vector, uint32_t cause,
+				uint32_t parameter)
 {
 	if (vector >= 0x10 && vector <= 0xFF) {
 		LOG_ERR("interrupt %u", vector);
@@ -360,7 +360,7 @@ void _Fault(z_arch_esf_t *esf, uint32_t old_sp)
 #endif
 
 	vector = Z_ARC_V2_ECR_VECTOR(ecr);
-	cause =  Z_ARC_V2_ECR_CODE(ecr);
+	cause = Z_ARC_V2_ECR_CODE(ecr);
 	parameter = Z_ARC_V2_ECR_PARAMETER(ecr);
 
 	/* exception raised by kernel */
@@ -371,7 +371,7 @@ void _Fault(z_arch_esf_t *esf, uint32_t old_sp)
 		 */
 #ifdef CONFIG_USERSPACE
 		if ((esf->status32 & _ARC_V2_STATUS32_U) &&
-			esf->r0 != K_ERR_STACK_CHK_FAIL) {
+		    esf->r0 != K_ERR_STACK_CHK_FAIL) {
 			esf->r0 = K_ERR_KERNEL_OOPS;
 		}
 #endif
@@ -400,8 +400,8 @@ void _Fault(z_arch_esf_t *esf, uint32_t old_sp)
 #endif
 
 #ifdef CONFIG_MPU_STACK_GUARD
-	if (vector == ARC_EV_PROT_V && ((parameter == 0x4) ||
-					(parameter == 0x24))) {
+	if (vector == ARC_EV_PROT_V &&
+	    ((parameter == 0x4) || (parameter == 0x24))) {
 		if (z_check_thread_stack_fail(exc_addr, old_sp)) {
 			z_arc_fatal_error(K_ERR_STACK_CHK_FAIL, esf);
 			return;

arch/arc/core/fault.c

@@ -26,7 +26,6 @@
 #include <irq.h>
 #include <sys/printk.h>
 
-
 /*
  * storage space for the interrupt stack of fast_irq
  */
@@ -47,38 +46,36 @@ void z_arc_firq_stack_set(void)
 {
 #ifdef CONFIG_SMP
 	char *firq_sp = Z_KERNEL_STACK_BUFFER(
-		  _firq_interrupt_stack[z_arc_v2_core_id()]) +
-		  CONFIG_ARC_FIRQ_STACK_SIZE;
+				_firq_interrupt_stack[z_arc_v2_core_id()]) +
+			CONFIG_ARC_FIRQ_STACK_SIZE;
 #else
 	char *firq_sp = Z_KERNEL_STACK_BUFFER(_firq_interrupt_stack) +
-		  CONFIG_ARC_FIRQ_STACK_SIZE;
+			CONFIG_ARC_FIRQ_STACK_SIZE;
 #endif
 
-/* the z_arc_firq_stack_set must be called when irq diasbled, as
+	/* the z_arc_firq_stack_set must be called when irq diasbled, as
  * it can be called not only in the init phase but also other places
  */
 	unsigned int key = arch_irq_lock();
 
-	__asm__ volatile (
-/* only ilink will not be banked, so use ilink as channel
+	__asm__ volatile(
+		/* only ilink will not be banked, so use ilink as channel
  * between 2 banks
  */
-	"mov %%ilink, %0\n\t"
-	"lr %0, [%1]\n\t"
-	"or %0, %0, %2\n\t"
-	"kflag %0\n\t"
-	"mov %%sp, %%ilink\n\t"
-/* switch back to bank0, use ilink to avoid the pollution of
+		"mov %%ilink, %0\n\t"
+		"lr %0, [%1]\n\t"
+		"or %0, %0, %2\n\t"
+		"kflag %0\n\t"
+		"mov %%sp, %%ilink\n\t"
+		/* switch back to bank0, use ilink to avoid the pollution of
  * bank1's gp regs.
  */
-	"lr %%ilink, [%1]\n\t"
-	"and %%ilink, %%ilink, %3\n\t"
-	"kflag %%ilink\n\t"
-	:
-	: "r"(firq_sp), "i"(_ARC_V2_STATUS32),
-	  "i"(_ARC_V2_STATUS32_RB(1)),
-	  "i"(~_ARC_V2_STATUS32_RB(7))
-	);
+		"lr %%ilink, [%1]\n\t"
+		"and %%ilink, %%ilink, %3\n\t"
+		"kflag %%ilink\n\t"
+		:
+		: "r"(firq_sp), "i"(_ARC_V2_STATUS32),
+		  "i"(_ARC_V2_STATUS32_RB(1)), "i"(~_ARC_V2_STATUS32_RB(7)));
 	arch_irq_unlock(key);
 }
 #endif
@@ -147,11 +144,10 @@ void z_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags)
  * left prio levels allocated to normal world
  */
 #if defined(CONFIG_ARC_SECURE_FIRMWARE)
-	prio = prio < ARC_N_IRQ_START_LEVEL ?
-		prio : (ARC_N_IRQ_START_LEVEL - 1);
+	prio = prio < ARC_N_IRQ_START_LEVEL ? prio :
+						    (ARC_N_IRQ_START_LEVEL - 1);
 #elif defined(CONFIG_ARC_NORMAL_FIRMWARE)
-	prio = prio < ARC_N_IRQ_START_LEVEL ?
-		 ARC_N_IRQ_START_LEVEL : prio;
+	prio = prio < ARC_N_IRQ_START_LEVEL ? ARC_N_IRQ_START_LEVEL : prio;
 #endif
 	z_arc_v2_irq_unit_prio_set(irq, prio);
 }

arch/arc/core/irq_manage.c

@@ -22,12 +22,11 @@ void z_irq_do_offload(void)
 
 void arch_irq_offload(irq_offload_routine_t routine, const void *parameter)
 {
-
 	offload_routine = routine;
 	offload_param = parameter;
 
-	__asm__ volatile ("trap_s %[id]"
-		:
-		: [id] "i"(_TRAP_S_SCALL_IRQ_OFFLOAD) : );
-
+	__asm__ volatile("trap_s %[id]"
+			 :
+			 : [id] "i"(_TRAP_S_SCALL_IRQ_OFFLOAD)
+			 :);
 }