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-46
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‎clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h

+3-3
Original file line numberDiff line numberDiff line change
@@ -397,9 +397,9 @@ class CIRBaseBuilderTy : public mlir::OpBuilder {
397397
return create<cir::MemCpyOp>(loc, dst, src, len);
398398
}
399399

400-
mlir::cir::SignBitOp createSignBit(mlir::Location loc, mlir::Value val) {
401-
auto resTy = mlir::cir::IntType::get(getContext(), 32, true);
402-
return create<mlir::cir::SignBitOp>(loc, resTy, val);
400+
cir::SignBitOp createSignBit(mlir::Location loc, mlir::Value val) {
401+
auto resTy = cir::IntType::get(getContext(), 32, true);
402+
return create<cir::SignBitOp>(loc, resTy, val);
403403
}
404404

405405
mlir::Value createSub(mlir::Value lhs, mlir::Value rhs, bool hasNUW = false,

‎clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp

+3-3
Original file line numberDiff line numberDiff line change
@@ -216,8 +216,8 @@ static mlir::Value emitFromInt(CIRGenFunction &CGF, mlir::Value v, QualType t,
216216
return v;
217217
}
218218

219-
static mlir::Value buildSignBit(mlir::Location loc, CIRGenFunction &CGF,
220-
mlir::Value val) {
219+
static mlir::Value emitSignBit(mlir::Location loc, CIRGenFunction &CGF,
220+
mlir::Value val) {
221221
assert(!::cir::MissingFeatures::isPPC_FP128Ty());
222222
auto ret = CGF.getBuilder().createSignBit(loc, val);
223223
return ret->getResult(0);
@@ -1710,7 +1710,7 @@ RValue CIRGenFunction::emitBuiltinExpr(const GlobalDecl GD, unsigned BuiltinID,
17101710
case Builtin::BI__builtin_signbitl: {
17111711
auto loc = getLoc(E->getBeginLoc());
17121712
return RValue::get(builder.createZExtOrBitCast(
1713-
loc, buildSignBit(loc, *this, buildScalarExpr(E->getArg(0))),
1713+
loc, emitSignBit(loc, *this, emitScalarExpr(E->getArg(0))),
17141714
ConvertType(E->getType())));
17151715
}
17161716

‎clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp

+31-25
Original file line numberDiff line numberDiff line change
@@ -4304,18 +4304,24 @@ class CIRAbsOpLowering : public mlir::OpConversionPattern<cir::AbsOp> {
43044304
return mlir::success();
43054305
}
43064306
};
4307-
class CIRSignBitOpLowering
4308-
: public mlir::OpConversionPattern<mlir::cir::SignBitOp> {
4307+
class CIRSignBitOpLowering : public mlir::OpConversionPattern<cir::SignBitOp> {
43094308
public:
4310-
using OpConversionPattern<mlir::cir::SignBitOp>::OpConversionPattern;
4309+
using OpConversionPattern<cir::SignBitOp>::OpConversionPattern;
43114310

43124311
mlir::LogicalResult
4313-
matchAndRewrite(mlir::cir::SignBitOp op, OpAdaptor adaptor,
4312+
matchAndRewrite(cir::SignBitOp op, OpAdaptor adaptor,
43144313
mlir::ConversionPatternRewriter &rewriter) const override {
43154314
assert(!::cir::MissingFeatures::isPPC_FP128Ty());
43164315

43174316
mlir::DataLayout layout(op->getParentOfType<mlir::ModuleOp>());
43184317
int width = layout.getTypeSizeInBits(op.getInput().getType());
4318+
if (auto longDoubleType =
4319+
mlir::dyn_cast<cir::LongDoubleType>(op.getInput().getType())) {
4320+
if (mlir::isa<cir::FP80Type>(longDoubleType.getUnderlying())) {
4321+
// see https://github.com/llvm/clangir/issues/1057
4322+
llvm_unreachable("NYI");
4323+
}
4324+
}
43194325
auto intTy = mlir::IntegerType::get(rewriter.getContext(), width);
43204326
auto bitcast = rewriter.create<mlir::LLVM::BitcastOp>(op->getLoc(), intTy,
43214327
adaptor.getInput());
@@ -4401,27 +4407,27 @@ std::unique_ptr<cir::LowerModule> prepareLowerModule(mlir::ModuleOp module) {
44014407
void prepareTypeConverter(mlir::LLVMTypeConverter &converter,
44024408
mlir::DataLayout &dataLayout,
44034409
cir::LowerModule *lowerModule) {
4404-
converter.addConversion([&,
4405-
lowerModule](cir::PointerType type) -> mlir::Type {
4406-
// Drop pointee type since LLVM dialect only allows opaque pointers.
4407-
4408-
auto addrSpace =
4409-
mlir::cast_if_present<cir::AddressSpaceAttr>(type.getAddrSpace());
4410-
// Null addrspace attribute indicates the default addrspace.
4411-
if (!addrSpace)
4412-
return mlir::LLVM::LLVMPointerType::get(type.getContext());
4413-
4414-
assert(lowerModule && "CIR AS map is not available");
4415-
// Pass through target addrspace and map CIR addrspace to LLVM addrspace by
4416-
// querying the target info.
4417-
unsigned targetAS =
4418-
addrSpace.isTarget()
4419-
? addrSpace.getTargetValue()
4420-
: lowerModule->getTargetLoweringInfo()
4421-
.getTargetAddrSpaceFromCIRAddrSpace(addrSpace);
4422-
4423-
return mlir::LLVM::LLVMPointerType::get(type.getContext(), targetAS);
4424-
});
4410+
converter.addConversion(
4411+
[&, lowerModule](cir::PointerType type) -> mlir::Type {
4412+
// Drop pointee type since LLVM dialect only allows opaque pointers.
4413+
4414+
auto addrSpace =
4415+
mlir::cast_if_present<cir::AddressSpaceAttr>(type.getAddrSpace());
4416+
// Null addrspace attribute indicates the default addrspace.
4417+
if (!addrSpace)
4418+
return mlir::LLVM::LLVMPointerType::get(type.getContext());
4419+
4420+
assert(lowerModule && "CIR AS map is not available");
4421+
// Pass through target addrspace and map CIR addrspace to LLVM addrspace
4422+
// by querying the target info.
4423+
unsigned targetAS =
4424+
addrSpace.isTarget()
4425+
? addrSpace.getTargetValue()
4426+
: lowerModule->getTargetLoweringInfo()
4427+
.getTargetAddrSpaceFromCIRAddrSpace(addrSpace);
4428+
4429+
return mlir::LLVM::LLVMPointerType::get(type.getContext(), targetAS);
4430+
});
44254431
converter.addConversion([&](cir::DataMemberType type) -> mlir::Type {
44264432
return mlir::IntegerType::get(type.getContext(),
44274433
dataLayout.getTypeSizeInBits(type));

‎clang/test/CIR/CodeGen/builtin-signbit.c

+6-15
Original file line numberDiff line numberDiff line change
@@ -4,31 +4,22 @@
44
// RUN: FileCheck --check-prefix=LLVM --input-file=%t.ll %s
55

66
void test_signbit_float(float val) {
7-
// CIR: test_signbit_float
8-
// LLVM: test_signbit_float
9-
__builtin_signbit(val);
7+
// CIR-LABEL: test_signbit_float
108
// CIR: %{{.+}} = cir.signbit %{{.+}} : !cir.float -> !s32i
9+
// LLVM-LABEL: test_signbit_float
1110
// LLVM: [[TMP1:%.*]] = bitcast float %{{.+}} to i32
1211
// LLVM: [[TMP2:%.*]] = icmp slt i32 [[TMP1]], 0
1312
// LLVM: %{{.+}} = zext i1 [[TMP2]] to i32
13+
__builtin_signbit(val);
1414
}
1515

1616
void test_signbit_double(double val) {
17-
// CIR: test_signbit_double
18-
// LLVM: test_signbit_double
19-
__builtin_signbitf(val);
17+
// CIR-LABEL: test_signbit_double
2018
// CIR: %{{.+}} = cir.signbit %{{.+}} : !cir.float -> !s32i
19+
// LLVM-LABEL: test_signbit_double
2120
// LLVM: [[CONV:%.*]] = fptrunc double %{{.+}} to float
2221
// LLVM: [[TMP1:%.*]] = bitcast float [[CONV]] to i32
2322
// LLVM: [[TMP2:%.*]] = icmp slt i32 [[TMP1]], 0
2423
// LLVM: %{{.+}} = zext i1 [[TMP2]] to i32
25-
}
26-
void test_signbit_long_double(long double val) {
27-
// CIR: test_signbit_long_double
28-
// LLVM: test_signbit_long_double
29-
__builtin_signbitl(val);
30-
// CIR: %{{.+}} = cir.signbit %{{.+}} : !cir.long_double<!cir.f80> -> !s32i
31-
// LLVM: [[TMP1:%.*]] = bitcast x86_fp80 %{{.+}} to i80
32-
// LLVM: [[TMP2:%.*]] = icmp slt i80 [[TMP1]], 0
33-
// LLVM: %{{.+}} = zext i1 [[TMP2]] to i32
24+
__builtin_signbitf(val);
3425
}

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