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[CIR][CIRGen][Builtin][Neon] Lower neon_vrnd32x (#1388)
Lower neon_vrnd32x
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-6
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2 files changed

+158
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‎clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp

+8-6
Original file line numberDiff line numberDiff line change
@@ -2619,6 +2619,14 @@ mlir::Value CIRGenFunction::emitCommonNeonBuiltinExpr(
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: "aarch64.neon.srhadd";
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break;
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}
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case NEON::BI__builtin_neon_vrnd32x_f32:
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case NEON::BI__builtin_neon_vrnd32xq_f32:
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case NEON::BI__builtin_neon_vrnd32x_f64:
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case NEON::BI__builtin_neon_vrnd32xq_f64: {
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intrincsName = "aarch64.neon.frint32x";
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argTypes.push_back(vTy);
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break;
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}
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case NEON::BI__builtin_neon_vshl_v:
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case NEON::BI__builtin_neon_vshlq_v: {
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return builder.create<cir::ShiftOp>(
@@ -4186,12 +4194,6 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned BuiltinID, const CallExpr *E,
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case NEON::BI__builtin_neon_vrndh_f16: {
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llvm_unreachable("NEON::BI__builtin_neon_vrndh_f16 NYI");
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}
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case NEON::BI__builtin_neon_vrnd32x_f32:
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case NEON::BI__builtin_neon_vrnd32xq_f32:
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case NEON::BI__builtin_neon_vrnd32x_f64:
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case NEON::BI__builtin_neon_vrnd32xq_f64: {
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llvm_unreachable("NEON::BI__builtin_neon_vrnd32xq_f64 NYI");
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}
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case NEON::BI__builtin_neon_vrnd32z_f32:
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case NEON::BI__builtin_neon_vrnd32zq_f32:
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case NEON::BI__builtin_neon_vrnd32z_f64:

‎clang/test/CIR/CodeGen/AArch64/v8.5a-neon-frint3264-intrinsic.c

+150
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,150 @@
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// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +fullfp16 -target-feature +v8.5a \
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// RUN: -fclangir -disable-O0-optnone \
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// RUN: -flax-vector-conversions=none -emit-cir -o %t.cir %s
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// RUN: FileCheck --check-prefix=CIR --input-file=%t.cir %s
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// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +fullfp16 -target-feature +v8.5a \
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// RUN: -fclangir -disable-O0-optnone \
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// RUN: -flax-vector-conversions=none -emit-llvm -fno-clangir-call-conv-lowering -o - %s \
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// RUN: | opt -S -passes=mem2reg,simplifycfg -o %t.ll
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// RUN: FileCheck --check-prefix=LLVM --input-file=%t.ll %s
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// REQUIRES: aarch64-registered-target || arm-registered-target
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// This test mimics clang/test/CodeGen/AArch64/v8.2a-neon-frint3264-intrinsics.c, which eventually
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// CIR shall be able to support fully. Since this is going to take some time to converge,
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// the unsupported/NYI code is commented out, so that we can incrementally improve this.
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// The NYI filecheck used contains the LLVM output from OG codegen that should guide the
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// correct result when implementing this into the CIR pipeline.
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#include <arm_neon.h>
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float32x2_t test_vrnd32x_f32(float32x2_t a) {
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return vrnd32x_f32(a);
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// CIR-LABEL: vrnd32x_f32
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// CIR: [[TMP0:%.*]] = cir.llvm.intrinsic "aarch64.neon.frint32x" {{.*}} : (!cir.vector<!cir.float x 2>) -> !cir.vector<!cir.float x 2>
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// LLVM-LABEL: @test_vrnd32x_f32
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// LLVM: [[RND:%.*]] = call <2 x float> @llvm.aarch64.neon.frint32x.v2f32(<2 x float> %0)
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// LLVM: ret <2 x float> [[RND]]
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}
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float32x4_t test_vrnd32xq_f32(float32x4_t a) {
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return vrnd32xq_f32(a);
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// CIR-LABEL: vrnd32xq_f32
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// CIR: [[TMP0:%.*]] = cir.llvm.intrinsic "aarch64.neon.frint32x" {{.*}} : (!cir.vector<!cir.float x 4>) -> !cir.vector<!cir.float x 4>
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// LLVM-LABEL: @test_vrnd32xq_f32
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// LLVM: [[RND:%.*]] = call <4 x float> @llvm.aarch64.neon.frint32x.v4f32(<4 x float> %0)
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// LLVM: ret <4 x float> [[RND]]
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}
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// CHECK-LABEL: test_vrnd32z_f32
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// CHECK: [[RND:%.*]] = call <2 x float> @llvm.aarch64.neon.frint32z.v2f32(<2 x float> %a)
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// CHECK: ret <2 x float> [[RND]]
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// float32x2_t test_vrnd32z_f32(float32x2_t a) {
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// return vrnd32z_f32(a);
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// }
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// CHECK-LABEL: test_vrnd32zq_f32
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// CHECK: [[RND:%.*]] = call <4 x float> @llvm.aarch64.neon.frint32z.v4f32(<4 x float> %a)
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// CHECK: ret <4 x float> [[RND]]
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// float32x4_t test_vrnd32zq_f32(float32x4_t a) {
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// return vrnd32zq_f32(a);
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// }
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// CHECK-LABEL: test_vrnd64x_f32
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// CHECK: [[RND:%.*]] = call <2 x float> @llvm.aarch64.neon.frint64x.v2f32(<2 x float> %a)
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// CHECK: ret <2 x float> [[RND]]
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// float32x2_t test_vrnd64x_f32(float32x2_t a) {
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// return vrnd64x_f32(a);
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// }
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// CHECK-LABEL: test_vrnd64xq_f32
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// CHECK: [[RND:%.*]] = call <4 x float> @llvm.aarch64.neon.frint64x.v4f32(<4 x float> %a)
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// CHECK: ret <4 x float> [[RND]]
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// float32x4_t test_vrnd64xq_f32(float32x4_t a) {
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// return vrnd64xq_f32(a);
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// }
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// CHECK-LABEL: test_vrnd64z_f32
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// CHECK: [[RND:%.*]] = call <2 x float> @llvm.aarch64.neon.frint64z.v2f32(<2 x float> %a)
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// CHECK: ret <2 x float> [[RND]]
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// float32x2_t test_vrnd64z_f32(float32x2_t a) {
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// return vrnd64z_f32(a);
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// }
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// CHECK-LABEL: test_vrnd64zq_f32
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// CHECK: [[RND:%.*]] = call <4 x float> @llvm.aarch64.neon.frint64z.v4f32(<4 x float> %a)
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// CHECK: ret <4 x float> [[RND]]
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// float32x4_t test_vrnd64zq_f32(float32x4_t a) {
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// return vrnd64zq_f32(a);
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// }
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float64x1_t test_vrnd32x_f64(float64x1_t a) {
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return vrnd32x_f64(a);
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// CIR-LABEL: vrnd32x_f64
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// CIR: [[TMP0:%.*]] = cir.llvm.intrinsic "aarch64.neon.frint32x" {{.*}} : (!cir.vector<!cir.double x 1>) -> !cir.vector<!cir.double x 1>
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// LLVM-LABEL: @test_vrnd32x_f64
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// LLVM: [[RND:%.*]] = call <1 x double> @llvm.aarch64.neon.frint32x.v1f64(<1 x double> %0)
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// LLVM: ret <1 x double> [[RND]]
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}
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float64x2_t test_vrnd32xq_f64(float64x2_t a) {
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return vrnd32xq_f64(a);
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// CIR-LABEL: vrnd32xq_f64
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// CIR: [[TMP0:%.*]] = cir.llvm.intrinsic "aarch64.neon.frint32x" {{.*}} : (!cir.vector<!cir.double x 2>) -> !cir.vector<!cir.double x 2>
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// LLVM-LABEL: @test_vrnd32xq_f64
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// LLVM: [[RND:%.*]] = call <2 x double> @llvm.aarch64.neon.frint32x.v2f64(<2 x double> %0)
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// LLVM: ret <2 x double> [[RND]]
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}
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// CHECK-LABEL: test_vrnd32z_f64
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// CHECK: [[RND:%.*]] = call <1 x double> @llvm.aarch64.neon.frint32z.v1f64(<1 x double> %a)
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// CHECK: ret <1 x double> [[RND]]
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// float64x1_t test_vrnd32z_f64(float64x1_t a) {
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// return vrnd32z_f64(a);
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// }
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// CHECK-LABEL: test_vrnd32zq_f64
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// CHECK: [[RND:%.*]] = call <2 x double> @llvm.aarch64.neon.frint32z.v2f64(<2 x double> %a)
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// CHECK: ret <2 x double> [[RND]]
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// float64x2_t test_vrnd32zq_f64(float64x2_t a) {
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// return vrnd32zq_f64(a);
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// }
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// CHECK-LABEL: test_vrnd64x_f64
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// CHECK: [[RND:%.*]] = call <1 x double> @llvm.aarch64.neon.frint64x.v1f64(<1 x double> %a)
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// CHECK: ret <1 x double> [[RND]]
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// float64x1_t test_vrnd64x_f64(float64x1_t a) {
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// return vrnd64x_f64(a);
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// }
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// CHECK-LABEL: test_vrnd64xq_f64
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// CHECK: [[RND:%.*]] = call <2 x double> @llvm.aarch64.neon.frint64x.v2f64(<2 x double> %a)
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// CHECK: ret <2 x double> [[RND]]
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// float64x2_t test_vrnd64xq_f64(float64x2_t a) {
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// return vrnd64xq_f64(a);
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// }
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// CHECK-LABEL: test_vrnd64z_f64
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// CHECK: [[RND:%.*]] = call <1 x double> @llvm.aarch64.neon.frint64z.v1f64(<1 x double> %a)
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// CHECK: ret <1 x double> [[RND]]
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// float64x1_t test_vrnd64z_f64(float64x1_t a) {
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// return vrnd64z_f64(a);
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// }
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// CHECK-LABEL: test_vrnd64zq_f64
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// CHECK: [[RND:%.*]] = call <2 x double> @llvm.aarch64.neon.frint64z.v2f64(<2 x double> %a)
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// CHECK: ret <2 x double> [[RND]]
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// float64x2_t test_vrnd64zq_f64(float64x2_t a) {
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// return vrnd64zq_f64(a);
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// }

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