Skip to content

Commit 85bc640

Browse files
authored
[CIR][CIRGen] Generate CIR for empty compound literal (#880)
as title.
1 parent 72b42af commit 85bc640

File tree

2 files changed

+21
-3
lines changed

2 files changed

+21
-3
lines changed

clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp

+3-3
Original file line numberDiff line numberDiff line change
@@ -340,8 +340,8 @@ class ScalarExprEmitter : public StmtVisitor<ScalarExprEmitter, mlir::Value> {
340340
}
341341

342342
mlir::Value VisitMemberExpr(MemberExpr *E);
343-
mlir::Value VisitCompoundLiteralEpxr(CompoundLiteralExpr *E) {
344-
llvm_unreachable("NYI");
343+
mlir::Value VisitCompoundLiteralExpr(CompoundLiteralExpr *E) {
344+
return buildLoadOfLValue(E);
345345
}
346346

347347
mlir::Value VisitInitListExpr(InitListExpr *E);
@@ -1930,7 +1930,7 @@ mlir::Value ScalarExprEmitter::VisitInitListExpr(InitListExpr *E) {
19301930

19311931
if (NumInitElements == 0) {
19321932
// C++11 value-initialization for the scalar.
1933-
llvm_unreachable("NYI");
1933+
return buildNullValue(E->getType(), CGF.getLoc(E->getExprLoc()));
19341934
}
19351935

19361936
return Visit(E->getInit(0));
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,18 @@
1+
// RUN: %clang_cc1 -triple aarch64-none-linux-android21 -fclangir -emit-cir %s -o %t.cir
2+
// RUN: FileCheck --check-prefix=CIR --input-file=%t.cir %s
3+
// RUN: %clang_cc1 -triple aarch64-none-linux-android21 -fclangir -emit-llvm %s -o %t.ll
4+
// RUN: FileCheck --input-file=%t.ll %s -check-prefix=LLVM
5+
6+
short b() { return (short){}; }
7+
8+
// CIR-LABEL: b
9+
// CIR: {{%.*}} = cir.alloca !s16i, !cir.ptr<!s16i>, [".compoundliteral"] {alignment = 2 : i64}
10+
11+
// LLVM-LABEL: b
12+
// LLVM: [[RET_P:%.*]] = alloca i16, i64 1, align 2
13+
// LLVM: [[LITERAL:%.*]] = alloca i16, i64 1, align 2
14+
// LLVM: store i16 0, ptr [[LITERAL]], align 2
15+
// LLVM: [[T0:%.*]] = load i16, ptr [[LITERAL]], align 2
16+
// LLVM: store i16 [[T0]], ptr [[RET_P]], align 2
17+
// LLVM: [[T1:%.*]] = load i16, ptr [[RET_P]], align 2
18+
// LLVM: ret i16 [[T1]]

0 commit comments

Comments
 (0)