[CIR][CIRGen][Builtin][Neon] Lower neon vld1_lane and vld1q_lane (#901)

just as title.

---------

Co-authored-by: Guojin He <[email protected]>

Author: ghehg

clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp

@@ -2971,7 +2971,7 @@ CIRGenFunction::buildAArch64BuiltinExpr(unsigned BuiltinID, const CallExpr *E,
           buildAArch64TblBuiltinExpr(*this, BuiltinID, E, Ops, Arch))
     return V;
 
-  mlir::Type VTy = Ty;
+  mlir::cir::VectorType VTy = Ty;
   llvm::SmallVector<mlir::Value, 4> args;
   switch (BuiltinID) {
   default:
@@ -3404,7 +3404,11 @@ CIRGenFunction::buildAArch64BuiltinExpr(unsigned BuiltinID, const CallExpr *E,
   }
   case NEON::BI__builtin_neon_vld1_lane_v:
   case NEON::BI__builtin_neon_vld1q_lane_v: {
-    llvm_unreachable("NYI");
+    Ops[1] = builder.createBitcast(Ops[1], VTy);
+    Ops[0] = builder.createAlignedLoad(Ops[0].getLoc(), VTy.getEltType(),
+                                       Ops[0], PtrOp0.getAlignment());
+    return builder.create<mlir::cir::VecInsertOp>(getLoc(E->getExprLoc()),
+                                                  Ops[1], Ops[0], Ops[2]);
   }
   case NEON::BI__builtin_neon_vldap1_lane_s64:
   case NEON::BI__builtin_neon_vldap1q_lane_s64: {