[CIR][CIRGen][AArch64] Make vrndns emit RoundEvenOp directly

Author: FantasqueX

clang/include/clang/CIR/Dialect/IR/CIROps.td

@@ -4787,6 +4787,7 @@ def Log2Op : UnaryFPToFPBuiltinOp<"log2", "Log2Op">;
 def NearbyintOp : UnaryFPToFPBuiltinOp<"nearbyint", "NearbyintOp">;
 def RintOp : UnaryFPToFPBuiltinOp<"rint", "RintOp">;
 def RoundOp : UnaryFPToFPBuiltinOp<"round", "RoundOp">;
+def RoundEvenOp : UnaryFPToFPBuiltinOp<"roundeven", "RoundEvenOp">;
 def SinOp : UnaryFPToFPBuiltinOp<"sin", "SinOp">;
 def SqrtOp : UnaryFPToFPBuiltinOp<"sqrt", "SqrtOp">;
 def TruncOp : UnaryFPToFPBuiltinOp<"trunc", "FTruncOp">;

clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp

@@ -2226,7 +2226,7 @@ static mlir::Value vecReduceIntValue(CIRGenFunction &cgf, mlir::Value val,
       loc, val, builder.getConstInt(loc, cgf.SizeTy, 0));
 }
 
-mlir::Value emitNeonCall(CIRGenBuilderTy &builder,
+static mlir::Value emitNeonCall(CIRGenBuilderTy &builder,
                          llvm::SmallVector<mlir::Type> argTypes,
                          llvm::SmallVectorImpl<mlir::Value> &args,
                          llvm::StringRef intrinsicName, mlir::Type funcResTy,
@@ -2261,6 +2261,41 @@ mlir::Value emitNeonCall(CIRGenBuilderTy &builder,
       .getResult();
 }
 
+template <typename Operation>
+static mlir::Value emitNeonCall(CIRGenBuilderTy &builder,
+                         llvm::SmallVector<mlir::Type> argTypes,
+                         llvm::SmallVectorImpl<mlir::Value> &args,
+                         mlir::Type funcResTy,
+                         mlir::Location loc,
+                         bool isConstrainedFPIntrinsic = false,
+                         unsigned shift = 0, bool rightshift = false) {
+  // TODO: Consider removing the following unreachable when we have
+  // emitConstrainedFPCall feature implemented
+  assert(!cir::MissingFeatures::emitConstrainedFPCall());
+  if (isConstrainedFPIntrinsic)
+    llvm_unreachable("isConstrainedFPIntrinsic NYI");
+
+  for (unsigned j = 0; j < argTypes.size(); ++j) {
+    if (isConstrainedFPIntrinsic) {
+      assert(!cir::MissingFeatures::emitConstrainedFPCall());
+    }
+    if (shift > 0 && shift == j) {
+      args[j] = emitNeonShiftVector(builder, args[j],
+                                    mlir::cast<cir::VectorType>(argTypes[j]),
+                                    loc, rightshift);
+    } else {
+      args[j] = builder.createBitcast(args[j], argTypes[j]);
+    }
+  }
+  if (isConstrainedFPIntrinsic) {
+    assert(!cir::MissingFeatures::emitConstrainedFPCall());
+    return nullptr;
+  }
+  return builder
+      .create<Operation>(loc, funcResTy, args)
+      .getResult();
+}
+
 /// This function `emitCommonNeonCallPattern0` implements a common way
 ///  to generate neon intrinsic call that has following pattern:
 ///  1. There is a need to cast result of the intrinsic call back to
@@ -4139,7 +4174,7 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned BuiltinID, const CallExpr *E,
   case NEON::BI__builtin_neon_vrndns_f32: {
     mlir::Value arg0 = emitScalarExpr(E->getArg(0));
     args.push_back(arg0);
-    return emitNeonCall(builder, {arg0.getType()}, args, "roundeven.f32",
+    return emitNeonCall<cir::RoundEvenOp>(builder, {arg0.getType()}, args,
                         getCIRGenModule().FloatTy, getLoc(E->getExprLoc()));
   }
   case NEON::BI__builtin_neon_vrndph_f16: {

clang/test/CIR/CodeGen/AArch64/neon-arith.c

@@ -23,7 +23,7 @@ float32_t test_vrndns_f32(float32_t a) {
 // CIR: cir.func internal private @vrndns_f32(%arg0: !cir.float {{.*}}) -> !cir.float
 // CIR: cir.store %arg0, [[ARG_SAVE:%.*]] : !cir.float, !cir.ptr<!cir.float> 
 // CIR: [[INTRIN_ARG:%.*]] = cir.load [[ARG_SAVE]] : !cir.ptr<!cir.float>, !cir.float 
-// CIR: {{%.*}} = cir.llvm.intrinsic "roundeven.f32" [[INTRIN_ARG]] : (!cir.float)
+// CIR: {{%.*}} = cir.roundeven [[INTRIN_ARG]] : !cir.float
 // CIR: cir.return {{%.*}} : !cir.float
 
 // CIR-LABEL: test_vrndns_f32