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[CIR] Change AtomicFenceOp's syncscope to OptionalAttr (#1429)
This PR make CIR's AtomicFenceOp similar to MLIR LLVMIR's FenceOp. MLIR LLVMIR FenceOp: https://github.com/llvm/clangir/blob/0bedc285dc6fbd8486877887939c742c2ddaecfa/mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td#L1925-L1947
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4 files changed

+27
-23
lines changed

4 files changed

+27
-23
lines changed

‎clang/include/clang/CIR/Dialect/IR/CIROps.td

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -5697,17 +5697,17 @@ def AtomicFence : CIR_Op<"atomic.fence"> {
56975697

56985698
Example:
56995699
```mlir
5700-
cir.atomic.fence system seq_cst
5701-
cir.atomic.fence single_thread seq_cst
5700+
cir.atomic.fence syncscope(system) seq_cst
5701+
cir.atomic.fence syncscope(single_thread) seq_cst
57025702
```
57035703

57045704
}];
5705+
let arguments = (ins Arg<MemOrder, "memory order">:$ordering,
5706+
OptionalAttr<MemScopeKind>:$syncscope);
57055707
let results = (outs);
5706-
let arguments = (ins Arg<MemScopeKind, "sync scope">:$sync_scope,
5707-
Arg<MemOrder, "memory order">:$ordering);
57085708

57095709
let assemblyFormat = [{
5710-
$sync_scope $ordering attr-dict
5710+
(`syncscope` `(` $syncscope^ `)`)? $ordering attr-dict
57115711
}];
57125712

57135713
let hasVerifier = 0;

‎clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -365,8 +365,9 @@ static mlir::Value makeAtomicFenceValue(CIRGenFunction &cgf,
365365
cir::MemOrder ordering =
366366
static_cast<cir::MemOrder>(constOrderingAttr.getUInt());
367367

368-
builder.create<cir::AtomicFence>(cgf.getLoc(expr->getSourceRange()),
369-
syncScope, ordering);
368+
builder.create<cir::AtomicFence>(
369+
cgf.getLoc(expr->getSourceRange()), ordering,
370+
MemScopeKindAttr::get(&cgf.getMLIRContext(), syncScope));
370371
}
371372

372373
return mlir::Value();

‎clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp

Lines changed: 13 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -405,6 +405,14 @@ static mlir::Value emitToMemory(mlir::ConversionPatternRewriter &rewriter,
405405
return value;
406406
}
407407

408+
std::optional<llvm::StringRef>
409+
getLLVMSyncScope(std::optional<cir::MemScopeKind> syncScope) {
410+
if (syncScope.has_value())
411+
return syncScope.value() == cir::MemScopeKind::MemScope_SingleThread
412+
? "singlethread"
413+
: "";
414+
return std::nullopt;
415+
}
408416
} // namespace
409417

410418
//===----------------------------------------------------------------------===//
@@ -3217,11 +3225,6 @@ mlir::LLVM::AtomicOrdering getLLVMAtomicOrder(cir::MemOrder memo) {
32173225
llvm_unreachable("shouldn't get here");
32183226
}
32193227

3220-
llvm::StringRef getLLVMSyncScope(cir::MemScopeKind syncScope) {
3221-
return syncScope == cir::MemScopeKind::MemScope_SingleThread ? "singlethread"
3222-
: "";
3223-
}
3224-
32253228
mlir::LogicalResult CIRToLLVMAtomicCmpXchgLowering::matchAndRewrite(
32263229
cir::AtomicCmpXchg op, OpAdaptor adaptor,
32273230
mlir::ConversionPatternRewriter &rewriter) const {
@@ -3232,8 +3235,7 @@ mlir::LogicalResult CIRToLLVMAtomicCmpXchgLowering::matchAndRewrite(
32323235
op.getLoc(), adaptor.getPtr(), expected, desired,
32333236
getLLVMAtomicOrder(adaptor.getSuccOrder()),
32343237
getLLVMAtomicOrder(adaptor.getFailOrder()));
3235-
if (const auto ss = adaptor.getSyncscope(); ss.has_value())
3236-
cmpxchg.setSyncscope(getLLVMSyncScope(ss.value()));
3238+
cmpxchg.setSyncscope(getLLVMSyncScope(adaptor.getSyncscope()));
32373239
cmpxchg.setAlignment(adaptor.getAlignment());
32383240
cmpxchg.setWeak(adaptor.getWeak());
32393241
cmpxchg.setVolatile_(adaptor.getIsVolatile());
@@ -3395,10 +3397,11 @@ mlir::LogicalResult CIRToLLVMAtomicFenceLowering::matchAndRewrite(
33953397
cir::AtomicFence op, OpAdaptor adaptor,
33963398
mlir::ConversionPatternRewriter &rewriter) const {
33973399
auto llvmOrder = getLLVMAtomicOrder(adaptor.getOrdering());
3398-
auto llvmSyncScope = getLLVMSyncScope(adaptor.getSyncScope());
33993400

3400-
rewriter.replaceOpWithNewOp<mlir::LLVM::FenceOp>(op, llvmOrder,
3401-
llvmSyncScope);
3401+
auto fence = rewriter.create<mlir::LLVM::FenceOp>(op.getLoc(), llvmOrder);
3402+
fence.setSyncscope(getLLVMSyncScope(adaptor.getSyncscope()));
3403+
3404+
rewriter.replaceOp(op, fence);
34023405

34033406
return mlir::success();
34043407
}

‎clang/test/CIR/CodeGen/atomic-thread-fence.c

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@ void applyThreadFence() {
1616
}
1717

1818
// CIR-LABEL: @applyThreadFence
19-
// CIR: cir.atomic.fence system seq_cst
19+
// CIR: cir.atomic.fence syncscope(system) seq_cst
2020
// CIR: cir.return
2121

2222
// LLVM-LABEL: @applyThreadFence
@@ -27,7 +27,7 @@ void applySignalFence() {
2727
__atomic_signal_fence(__ATOMIC_SEQ_CST);
2828
}
2929
// CIR-LABEL: @applySignalFence
30-
// CIR: cir.atomic.fence single_thread seq_cst
30+
// CIR: cir.atomic.fence syncscope(single_thread) seq_cst
3131
// CIR: cir.return
3232

3333
// LLVM-LABEL: @applySignalFence
@@ -40,7 +40,7 @@ void modifyWithThreadFence(DataPtr d) {
4040
}
4141
// CIR-LABEL: @modifyWithThreadFence
4242
// CIR: %[[DATA:.*]] = cir.alloca !cir.ptr<!ty_Data>, !cir.ptr<!cir.ptr<!ty_Data>>, ["d", init] {alignment = 8 : i64}
43-
// CIR: cir.atomic.fence system seq_cst
43+
// CIR: cir.atomic.fence syncscope(system) seq_cst
4444
// CIR: %[[VAL_42:.*]] = cir.const #cir.int<42> : !s32i
4545
// CIR: %[[LOAD_DATA:.*]] = cir.load %[[DATA]] : !cir.ptr<!cir.ptr<!ty_Data>>, !cir.ptr<!ty_Data>
4646
// CIR: %[[DATA_VALUE:.*]] = cir.get_member %[[LOAD_DATA]][0] {name = "value"} : !cir.ptr<!ty_Data> -> !cir.ptr<!s32i>
@@ -61,7 +61,7 @@ void modifyWithSignalFence(DataPtr d) {
6161
}
6262
// CIR-LABEL: @modifyWithSignalFence
6363
// CIR: %[[DATA:.*]] = cir.alloca !cir.ptr<!ty_Data>, !cir.ptr<!cir.ptr<!ty_Data>>, ["d", init] {alignment = 8 : i64}
64-
// CIR: cir.atomic.fence single_thread seq_cst
64+
// CIR: cir.atomic.fence syncscope(single_thread) seq_cst
6565
// CIR: %[[VAL_42:.*]] = cir.const #cir.int<24> : !s32i
6666
// CIR: %[[LOAD_DATA:.*]] = cir.load %[[DATA]] : !cir.ptr<!cir.ptr<!ty_Data>>, !cir.ptr<!ty_Data>
6767
// CIR: %[[DATA_VALUE:.*]] = cir.get_member %[[LOAD_DATA]][0] {name = "value"} : !cir.ptr<!ty_Data> -> !cir.ptr<!s32i>
@@ -83,7 +83,7 @@ void loadWithThreadFence(DataPtr d) {
8383
// CIR-LABEL: @loadWithThreadFence
8484
// CIR: %[[DATA:.*]] = cir.alloca !cir.ptr<!ty_Data>, !cir.ptr<!cir.ptr<!ty_Data>>, ["d", init] {alignment = 8 : i64}
8585
// CIR: %[[ATOMIC_TEMP:.*]] = cir.alloca !cir.ptr<!void>, !cir.ptr<!cir.ptr<!void>>, ["atomic-temp"] {alignment = 8 : i64}
86-
// CIR: cir.atomic.fence system seq_cst
86+
// CIR: cir.atomic.fence syncscope(system) seq_cst
8787
// CIR: %[[LOAD_DATA:.*]] = cir.load %[[DATA]] : !cir.ptr<!cir.ptr<!ty_Data>>, !cir.ptr<!ty_Data>
8888
// CIR: %[[DATA_VALUE:.*]] = cir.get_member %[[LOAD_DATA]][1] {name = "ptr"} : !cir.ptr<!ty_Data> -> !cir.ptr<!cir.ptr<!void>>
8989
// CIR: %[[CASTED_DATA_VALUE:.*]] = cir.cast(bitcast, %[[DATA_VALUE]] : !cir.ptr<!cir.ptr<!void>>), !cir.ptr<!u64i>
@@ -112,7 +112,7 @@ void loadWithSignalFence(DataPtr d) {
112112
// CIR-LABEL: @loadWithSignalFence
113113
// CIR: %[[DATA:.*]] = cir.alloca !cir.ptr<!ty_Data>, !cir.ptr<!cir.ptr<!ty_Data>>, ["d", init] {alignment = 8 : i64}
114114
// CIR: %[[ATOMIC_TEMP:.*]] = cir.alloca !cir.ptr<!void>, !cir.ptr<!cir.ptr<!void>>, ["atomic-temp"] {alignment = 8 : i64}
115-
// CIR: cir.atomic.fence single_thread seq_cst
115+
// CIR: cir.atomic.fence syncscope(single_thread) seq_cst
116116
// CIR: %[[LOAD_DATA:.*]] = cir.load %[[DATA]] : !cir.ptr<!cir.ptr<!ty_Data>>, !cir.ptr<!ty_Data>
117117
// CIR: %[[DATA_PTR:.*]] = cir.get_member %[[LOAD_DATA]][1] {name = "ptr"} : !cir.ptr<!ty_Data> -> !cir.ptr<!cir.ptr<!void>>
118118
// CIR: %[[CASTED_DATA_PTR:.*]] = cir.cast(bitcast, %[[DATA_PTR]] : !cir.ptr<!cir.ptr<!void>>), !cir.ptr<!u64i>

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