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[ARM] Tests for various NEON vector compares. NFC
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‎llvm/test/CodeGen/ARM/vcmpz.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=armv8-eabi -mattr=+neon | FileCheck %s
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define arm_aapcs_vfpcc <4 x i32> @vcmpz_eq(<4 x i32> %0, <4 x i32> %b) {
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; CHECK-LABEL: vcmpz_eq:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vceq.i32 q0, q0, q1
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; CHECK-NEXT: bx lr
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%2 = icmp eq <4 x i32> %0, %b
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%3 = sext <4 x i1> %2 to <4 x i32>
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ret <4 x i32> %3
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}
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define arm_aapcs_vfpcc <4 x i32> @vcmpz_ne(<4 x i32> %0, <4 x i32> %b) {
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; CHECK-LABEL: vcmpz_ne:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vceq.i32 q8, q0, q1
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; CHECK-NEXT: vmvn q0, q8
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; CHECK-NEXT: bx lr
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%2 = icmp ne <4 x i32> %0, %b
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%3 = sext <4 x i1> %2 to <4 x i32>
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ret <4 x i32> %3
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}
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define arm_aapcs_vfpcc <4 x i32> @vcmpz_slt(<4 x i32> %0, <4 x i32> %b) {
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; CHECK-LABEL: vcmpz_slt:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vcgt.s32 q0, q1, q0
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; CHECK-NEXT: bx lr
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%2 = icmp slt <4 x i32> %0, %b
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%3 = sext <4 x i1> %2 to <4 x i32>
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ret <4 x i32> %3
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}
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define arm_aapcs_vfpcc <4 x i32> @vcmpz_sle(<4 x i32> %0, <4 x i32> %b) {
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; CHECK-LABEL: vcmpz_sle:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vcge.s32 q0, q1, q0
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; CHECK-NEXT: bx lr
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%2 = icmp sle <4 x i32> %0, %b
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%3 = sext <4 x i1> %2 to <4 x i32>
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ret <4 x i32> %3
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}
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define arm_aapcs_vfpcc <4 x i32> @vcmpz_sgt(<4 x i32> %0, <4 x i32> %b) {
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; CHECK-LABEL: vcmpz_sgt:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vcgt.s32 q0, q0, q1
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; CHECK-NEXT: bx lr
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%2 = icmp sgt <4 x i32> %0, %b
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%3 = sext <4 x i1> %2 to <4 x i32>
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ret <4 x i32> %3
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}
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define arm_aapcs_vfpcc <4 x i32> @vcmpz_sge(<4 x i32> %0, <4 x i32> %b) {
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; CHECK-LABEL: vcmpz_sge:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vcge.s32 q0, q0, q1
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; CHECK-NEXT: bx lr
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%2 = icmp sge <4 x i32> %0, %b
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%3 = sext <4 x i1> %2 to <4 x i32>
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ret <4 x i32> %3
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}
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define arm_aapcs_vfpcc <4 x i32> @vcmpz_ult(<4 x i32> %0, <4 x i32> %b) {
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; CHECK-LABEL: vcmpz_ult:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vcgt.u32 q0, q1, q0
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; CHECK-NEXT: bx lr
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%2 = icmp ult <4 x i32> %0, %b
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%3 = sext <4 x i1> %2 to <4 x i32>
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ret <4 x i32> %3
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}
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define arm_aapcs_vfpcc <4 x i32> @vcmpz_ule(<4 x i32> %0, <4 x i32> %b) {
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; CHECK-LABEL: vcmpz_ule:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vcge.u32 q0, q1, q0
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; CHECK-NEXT: bx lr
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%2 = icmp ule <4 x i32> %0, %b
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%3 = sext <4 x i1> %2 to <4 x i32>
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ret <4 x i32> %3
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}
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define arm_aapcs_vfpcc <4 x i32> @vcmpz_ugt(<4 x i32> %0, <4 x i32> %b) {
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; CHECK-LABEL: vcmpz_ugt:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vcgt.u32 q0, q0, q1
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; CHECK-NEXT: bx lr
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%2 = icmp ugt <4 x i32> %0, %b
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%3 = sext <4 x i1> %2 to <4 x i32>
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ret <4 x i32> %3
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}
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define arm_aapcs_vfpcc <4 x i32> @vcmpz_uge(<4 x i32> %0, <4 x i32> %b) {
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; CHECK-LABEL: vcmpz_uge:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vcge.u32 q0, q0, q1
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; CHECK-NEXT: bx lr
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%2 = icmp uge <4 x i32> %0, %b
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%3 = sext <4 x i1> %2 to <4 x i32>
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ret <4 x i32> %3
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}
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define arm_aapcs_vfpcc <4 x i32> @vcmpz_zr_eq(<4 x i32> %0) {
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; CHECK-LABEL: vcmpz_zr_eq:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vceq.i32 q0, q0, #0
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; CHECK-NEXT: bx lr
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%2 = icmp eq <4 x i32> %0, zeroinitializer
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%3 = sext <4 x i1> %2 to <4 x i32>
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ret <4 x i32> %3
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}
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define arm_aapcs_vfpcc <4 x i32> @vcmpz_zr_ne(<4 x i32> %0) {
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; CHECK-LABEL: vcmpz_zr_ne:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vceq.i32 q8, q0, #0
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; CHECK-NEXT: vmvn q0, q8
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; CHECK-NEXT: bx lr
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%2 = icmp ne <4 x i32> %0, zeroinitializer
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%3 = sext <4 x i1> %2 to <4 x i32>
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ret <4 x i32> %3
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}
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define arm_aapcs_vfpcc <4 x i32> @vcmpz_zr_slt(<4 x i32> %0) {
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; CHECK-LABEL: vcmpz_zr_slt:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vclt.s32 q0, q0, #0
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; CHECK-NEXT: bx lr
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%2 = icmp slt <4 x i32> %0, zeroinitializer
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%3 = sext <4 x i1> %2 to <4 x i32>
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ret <4 x i32> %3
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}
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define arm_aapcs_vfpcc <4 x i32> @vcmpz_zr_sle(<4 x i32> %0) {
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; CHECK-LABEL: vcmpz_zr_sle:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vcle.s32 q0, q0, #0
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; CHECK-NEXT: bx lr
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%2 = icmp sle <4 x i32> %0, zeroinitializer
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%3 = sext <4 x i1> %2 to <4 x i32>
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ret <4 x i32> %3
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}
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define arm_aapcs_vfpcc <4 x i32> @vcmpz_zr_sgt(<4 x i32> %0) {
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; CHECK-LABEL: vcmpz_zr_sgt:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vcgt.s32 q0, q0, #0
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; CHECK-NEXT: bx lr
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%2 = icmp sgt <4 x i32> %0, zeroinitializer
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%3 = sext <4 x i1> %2 to <4 x i32>
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ret <4 x i32> %3
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}
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define arm_aapcs_vfpcc <4 x i32> @vcmpz_zr_sge(<4 x i32> %0) {
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; CHECK-LABEL: vcmpz_zr_sge:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vcge.s32 q0, q0, #0
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; CHECK-NEXT: bx lr
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%2 = icmp sge <4 x i32> %0, zeroinitializer
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%3 = sext <4 x i1> %2 to <4 x i32>
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ret <4 x i32> %3
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}
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define arm_aapcs_vfpcc <4 x i32> @vcmpz_zr_ult(<4 x i32> %0) {
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; CHECK-LABEL: vcmpz_zr_ult:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vmov.i32 q0, #0x0
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; CHECK-NEXT: bx lr
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%2 = icmp ult <4 x i32> %0, zeroinitializer
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%3 = sext <4 x i1> %2 to <4 x i32>
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ret <4 x i32> %3
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}
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;define arm_aapcs_vfpcc <4 x i32> @vcmpz_zr_ule(<4 x i32> %0) {
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; %2 = icmp ule <4 x i32> %0, zeroinitializer
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; %3 = sext <4 x i1> %2 to <4 x i32>
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; ret <4 x i32> %3
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;}
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define arm_aapcs_vfpcc <4 x i32> @vcmpz_zr_ugt(<4 x i32> %0) {
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; CHECK-LABEL: vcmpz_zr_ugt:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vceq.i32 q8, q0, #0
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; CHECK-NEXT: vmvn q0, q8
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; CHECK-NEXT: bx lr
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%2 = icmp ugt <4 x i32> %0, zeroinitializer
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%3 = sext <4 x i1> %2 to <4 x i32>
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ret <4 x i32> %3
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}
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define arm_aapcs_vfpcc <4 x i32> @vcmpz_zr_uge(<4 x i32> %0) {
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; CHECK-LABEL: vcmpz_zr_uge:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vmov.i8 q0, #0xff
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; CHECK-NEXT: bx lr
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%2 = icmp uge <4 x i32> %0, zeroinitializer
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%3 = sext <4 x i1> %2 to <4 x i32>
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ret <4 x i32> %3
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}
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define arm_aapcs_vfpcc <4 x i32> @vcmpz_zl_eq(<4 x i32> %0) {
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; CHECK-LABEL: vcmpz_zl_eq:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vceq.i32 q0, q0, #0
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; CHECK-NEXT: bx lr
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%2 = icmp eq <4 x i32> zeroinitializer, %0
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%3 = sext <4 x i1> %2 to <4 x i32>
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ret <4 x i32> %3
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}
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define arm_aapcs_vfpcc <4 x i32> @vcmpz_zl_ne(<4 x i32> %0) {
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; CHECK-LABEL: vcmpz_zl_ne:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vceq.i32 q8, q0, #0
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; CHECK-NEXT: vmvn q0, q8
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; CHECK-NEXT: bx lr
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%2 = icmp ne <4 x i32> zeroinitializer, %0
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%3 = sext <4 x i1> %2 to <4 x i32>
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ret <4 x i32> %3
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}
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define arm_aapcs_vfpcc <4 x i32> @vcmpz_zl_slt(<4 x i32> %0) {
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; CHECK-LABEL: vcmpz_zl_slt:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vcgt.s32 q0, q0, #0
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; CHECK-NEXT: bx lr
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%2 = icmp slt <4 x i32> zeroinitializer, %0
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%3 = sext <4 x i1> %2 to <4 x i32>
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ret <4 x i32> %3
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}
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define arm_aapcs_vfpcc <4 x i32> @vcmpz_zl_sle(<4 x i32> %0) {
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; CHECK-LABEL: vcmpz_zl_sle:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vcge.s32 q0, q0, #0
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; CHECK-NEXT: bx lr
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%2 = icmp sle <4 x i32> zeroinitializer, %0
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%3 = sext <4 x i1> %2 to <4 x i32>
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ret <4 x i32> %3
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}
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define arm_aapcs_vfpcc <4 x i32> @vcmpz_zl_sgt(<4 x i32> %0) {
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; CHECK-LABEL: vcmpz_zl_sgt:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vclt.s32 q0, q0, #0
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; CHECK-NEXT: bx lr
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%2 = icmp sgt <4 x i32> zeroinitializer, %0
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%3 = sext <4 x i1> %2 to <4 x i32>
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ret <4 x i32> %3
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}
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define arm_aapcs_vfpcc <4 x i32> @vcmpz_zl_sge(<4 x i32> %0) {
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; CHECK-LABEL: vcmpz_zl_sge:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vcle.s32 q0, q0, #0
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; CHECK-NEXT: bx lr
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%2 = icmp sge <4 x i32> zeroinitializer, %0
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%3 = sext <4 x i1> %2 to <4 x i32>
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ret <4 x i32> %3
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}
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define arm_aapcs_vfpcc <4 x i32> @vcmpz_zl_ult(<4 x i32> %0) {
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; CHECK-LABEL: vcmpz_zl_ult:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vceq.i32 q8, q0, #0
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; CHECK-NEXT: vmvn q0, q8
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; CHECK-NEXT: bx lr
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%2 = icmp ult <4 x i32> zeroinitializer, %0
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%3 = sext <4 x i1> %2 to <4 x i32>
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ret <4 x i32> %3
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}
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define arm_aapcs_vfpcc <4 x i32> @vcmpz_zl_ule(<4 x i32> %0) {
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; CHECK-LABEL: vcmpz_zl_ule:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vmov.i8 q0, #0xff
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; CHECK-NEXT: bx lr
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%2 = icmp ule <4 x i32> zeroinitializer, %0
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%3 = sext <4 x i1> %2 to <4 x i32>
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ret <4 x i32> %3
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}
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define arm_aapcs_vfpcc <4 x i32> @vcmpz_zl_ugt(<4 x i32> %0) {
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; CHECK-LABEL: vcmpz_zl_ugt:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vmov.i32 q0, #0x0
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; CHECK-NEXT: bx lr
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%2 = icmp ugt <4 x i32> zeroinitializer, %0
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%3 = sext <4 x i1> %2 to <4 x i32>
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ret <4 x i32> %3
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}
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;define arm_aapcs_vfpcc <4 x i32> @vcmpz_zl_uge(<4 x i32> %0) {
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; %2 = icmp uge <4 x i32> zeroinitializer, %0
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; %3 = sext <4 x i1> %2 to <4 x i32>
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; ret <4 x i32> %3
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;}

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