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[CIR][CIRGen][Builtin][Neon] Lower neon_vrshrn_n to llvm intrinsic call (#982)
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2 files changed

+59
-33
lines changed

2 files changed

+59
-33
lines changed

clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3116,7 +3116,12 @@ CIRGenFunction::buildAArch64BuiltinExpr(unsigned BuiltinID, const CallExpr *E,
31163116
case NEON::BI__builtin_neon_vqshrn_n_v:
31173117
llvm_unreachable("NYI");
31183118
case NEON::BI__builtin_neon_vrshrn_n_v:
3119-
llvm_unreachable("NYI");
3119+
return buildNeonCall(
3120+
builder,
3121+
{builder.getExtendedElementVectorType(
3122+
vTy, mlir::cast<mlir::cir::IntType>(vTy.getEltType()).isSigned()),
3123+
SInt32Ty},
3124+
Ops, "llvm.aarch64.neon.rshrn", ty, getLoc(E->getExprLoc()));
31203125
case NEON::BI__builtin_neon_vqrshrn_n_v:
31213126
llvm_unreachable("NYI");
31223127
case NEON::BI__builtin_neon_vrndah_f16: {

clang/test/CIR/CodeGen/AArch64/neon.c

Lines changed: 53 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -5900,41 +5900,62 @@ int8x8_t test_vqadd_s8(int8x8_t a, int8x8_t b) {
59005900
// return vrshrn_n_s32(a, 9);
59015901
// }
59025902

5903-
// NYI-LABEL: @test_vrshrn_n_s64(
5904-
// NYI: [[TMP0:%.*]] = bitcast <2 x i64> %a to <16 x i8>
5905-
// NYI: [[VRSHRN_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
5906-
// NYI: [[VRSHRN_N1:%.*]] = call <2 x i32> @llvm.aarch64.neon.rshrn.v2i32(<2 x i64> [[VRSHRN_N]], i32 19)
5907-
// NYI: ret <2 x i32> [[VRSHRN_N1]]
5908-
// int32x2_t test_vrshrn_n_s64(int64x2_t a) {
5909-
// return vrshrn_n_s64(a, 19);
5910-
// }
5903+
int32x2_t test_vrshrn_n_s64(int64x2_t a) {
5904+
return vrshrn_n_s64(a, 19);
5905+
5906+
// CIR-LABEL: vrshrn_n_s64
5907+
// CIR: {{%.*}} = cir.llvm.intrinsic "llvm.aarch64.neon.rshrn" {{%.*}}, {{%.*}} :
5908+
// CIR-SAME: (!cir.vector<!s64i x 2>, !s32i) -> !cir.vector<!s32i x 2>
5909+
5910+
// LLVM: {{.*}}test_vrshrn_n_s64(<2 x i64>{{.*}}[[A:%.*]])
5911+
// LLVM: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>
5912+
// LLVM: [[VRSHRN_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
5913+
// LLVM: [[VRSHRN_N1:%.*]] = call <2 x i32> @llvm.aarch64.neon.rshrn.v2i32(<2 x i64> [[VRSHRN_N]], i32 19)
5914+
// LLVM: ret <2 x i32> [[VRSHRN_N1]]
5915+
}
59115916

5912-
// NYI-LABEL: @test_vrshrn_n_u16(
5913-
// NYI: [[TMP0:%.*]] = bitcast <8 x i16> %a to <16 x i8>
5914-
// NYI: [[VRSHRN_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>
5915-
// NYI: [[VRSHRN_N1:%.*]] = call <8 x i8> @llvm.aarch64.neon.rshrn.v8i8(<8 x i16> [[VRSHRN_N]], i32 3)
5916-
// NYI: ret <8 x i8> [[VRSHRN_N1]]
5917-
// uint8x8_t test_vrshrn_n_u16(uint16x8_t a) {
5918-
// return vrshrn_n_u16(a, 3);
5919-
// }
5917+
uint8x8_t test_vrshrn_n_u16(uint16x8_t a) {
5918+
return vrshrn_n_u16(a, 3);
59205919

5921-
// NYI-LABEL: @test_vrshrn_n_u32(
5922-
// NYI: [[TMP0:%.*]] = bitcast <4 x i32> %a to <16 x i8>
5923-
// NYI: [[VRSHRN_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>
5924-
// NYI: [[VRSHRN_N1:%.*]] = call <4 x i16> @llvm.aarch64.neon.rshrn.v4i16(<4 x i32> [[VRSHRN_N]], i32 9)
5925-
// NYI: ret <4 x i16> [[VRSHRN_N1]]
5926-
// uint16x4_t test_vrshrn_n_u32(uint32x4_t a) {
5927-
// return vrshrn_n_u32(a, 9);
5928-
// }
5920+
// CIR-LABEL: vrshrn_n_u16
5921+
// CIR: {{%.*}} = cir.llvm.intrinsic "llvm.aarch64.neon.rshrn" {{%.*}}, {{%.*}} :
5922+
// CIR-SAME: (!cir.vector<!u16i x 8>, !s32i) -> !cir.vector<!u8i x 8>
59295923

5930-
// NYI-LABEL: @test_vrshrn_n_u64(
5931-
// NYI: [[TMP0:%.*]] = bitcast <2 x i64> %a to <16 x i8>
5932-
// NYI: [[VRSHRN_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
5933-
// NYI: [[VRSHRN_N1:%.*]] = call <2 x i32> @llvm.aarch64.neon.rshrn.v2i32(<2 x i64> [[VRSHRN_N]], i32 19)
5934-
// NYI: ret <2 x i32> [[VRSHRN_N1]]
5935-
// uint32x2_t test_vrshrn_n_u64(uint64x2_t a) {
5936-
// return vrshrn_n_u64(a, 19);
5937-
// }
5924+
// LLVM: {{.*}}test_vrshrn_n_u16(<8 x i16>{{.*}}[[A:%.*]])
5925+
// LLVM: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>
5926+
// LLVM: [[VRSHRN_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>
5927+
// LLVM: [[VRSHRN_N1:%.*]] = call <8 x i8> @llvm.aarch64.neon.rshrn.v8i8(<8 x i16> [[VRSHRN_N]], i32 3)
5928+
// LLVM: ret <8 x i8> [[VRSHRN_N1]]
5929+
}
5930+
5931+
uint16x4_t test_vrshrn_n_u32(uint32x4_t a) {
5932+
return vrshrn_n_u32(a, 9);
5933+
5934+
// CIR-LABEL: vrshrn_n_u32
5935+
// CIR: {{%.*}} = cir.llvm.intrinsic "llvm.aarch64.neon.rshrn" {{%.*}}, {{%.*}} :
5936+
// CIR-SAME: (!cir.vector<!u32i x 4>, !s32i) -> !cir.vector<!u16i x 4>
5937+
5938+
// LLVM: {{.*}}vrshrn_n_u32(<4 x i32>{{.*}}[[A:%.*]])
5939+
// LLVM: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>
5940+
// LLVM: [[VRSHRN_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>
5941+
// LLVM: [[VRSHRN_N1:%.*]] = call <4 x i16> @llvm.aarch64.neon.rshrn.v4i16(<4 x i32> [[VRSHRN_N]], i32 9)
5942+
// LLVM: ret <4 x i16> [[VRSHRN_N1]]
5943+
}
5944+
5945+
uint32x2_t test_vrshrn_n_u64(uint64x2_t a) {
5946+
return vrshrn_n_u64(a, 19);
5947+
5948+
// CIR-LABEL: vrshrn_n_u64
5949+
// CIR: {{%.*}} = cir.llvm.intrinsic "llvm.aarch64.neon.rshrn" {{%.*}}, {{%.*}} :
5950+
// CIR-SAME: (!cir.vector<!u64i x 2>, !s32i) -> !cir.vector<!u32i x 2>
5951+
5952+
// LLVM: {{.*}}test_vrshrn_n_u64(<2 x i64>{{.*}}[[A:%.*]])
5953+
// LLVM: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>
5954+
// LLVM: [[VRSHRN_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
5955+
// LLVM: [[VRSHRN_N1:%.*]] = call <2 x i32> @llvm.aarch64.neon.rshrn.v2i32(<2 x i64> [[VRSHRN_N]], i32 19)
5956+
// LLVM: ret <2 x i32> [[VRSHRN_N1]]
5957+
5958+
}
59385959

59395960
// NYI-LABEL: @test_vrshrn_high_n_s16(
59405961
// NYI: [[TMP0:%.*]] = bitcast <8 x i16> %b to <16 x i8>

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