From 83b525519c7e157a95da416cd433572c38d7dea8 Mon Sep 17 00:00:00 2001
From: AmrDeveloper <amr96@programmer.net>
Date: Mon, 24 Feb 2025 20:58:04 +0100
Subject: [PATCH] [CIR][CIRGen][Builtin][Neon] Lower vrnd64z and vrnd64zq

---
 .../lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp  |  8 +++
 .../AArch64/v8.5a-neon-frint3264-intrinsic.c  | 52 ++++++++++++++-----
 2 files changed, 48 insertions(+), 12 deletions(-)

diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
index bfbe64048caf..634bc6374fa4 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
@@ -2582,6 +2582,14 @@ mlir::Value CIRGenFunction::emitCommonNeonBuiltinExpr(
     argTypes.push_back(vTy);
     break;
   }
+  case NEON::BI__builtin_neon_vrnd64z_f32:
+  case NEON::BI__builtin_neon_vrnd64zq_f32:
+  case NEON::BI__builtin_neon_vrnd64z_f64:
+  case NEON::BI__builtin_neon_vrnd64zq_f64: {
+    intrincsName = "aarch64.neon.frint64z";
+    argTypes.push_back(vTy);
+    break;
+  }
   case NEON::BI__builtin_neon_vshl_v:
   case NEON::BI__builtin_neon_vshlq_v: {
     return builder.create<cir::ShiftOp>(
diff --git a/clang/test/CIR/CodeGen/AArch64/v8.5a-neon-frint3264-intrinsic.c b/clang/test/CIR/CodeGen/AArch64/v8.5a-neon-frint3264-intrinsic.c
index b812580d3565..31d4f2dc9fea 100644
--- a/clang/test/CIR/CodeGen/AArch64/v8.5a-neon-frint3264-intrinsic.c
+++ b/clang/test/CIR/CodeGen/AArch64/v8.5a-neon-frint3264-intrinsic.c
@@ -95,16 +95,30 @@ float32x4_t test_vrnd64xq_f32(float32x4_t a) {
 // CHECK-LABEL: test_vrnd64z_f32
 // CHECK:  [[RND:%.*]] =  call <2 x float> @llvm.aarch64.neon.frint64z.v2f32(<2 x float> %a)
 // CHECK:  ret <2 x float> [[RND]]
-// float32x2_t test_vrnd64z_f32(float32x2_t a) {
-//   return vrnd64z_f32(a);
-// }
+float32x2_t test_vrnd64z_f32(float32x2_t a) {
+  return vrnd64z_f32(a);
+
+  // CIR-LABEL: vrnd64z_f32
+  // CIR: [[TMP0:%.*]] = cir.llvm.intrinsic "aarch64.neon.frint64z" {{.*}} : (!cir.vector<!cir.float x 2>) -> !cir.vector<!cir.float x 2>
+
+  // LLVM-LABEL: @test_vrnd64z_f32
+  // LLVM:  [[RND:%.*]] =  call <2 x float> @llvm.aarch64.neon.frint64z.v2f32(<2 x float> %0)
+  // LLVM:  ret <2 x float> [[RND]]
+}
 
 // CHECK-LABEL: test_vrnd64zq_f32
 // CHECK:  [[RND:%.*]] =  call <4 x float> @llvm.aarch64.neon.frint64z.v4f32(<4 x float> %a)
 // CHECK:  ret <4 x float> [[RND]]
-// float32x4_t test_vrnd64zq_f32(float32x4_t a) {
-//   return vrnd64zq_f32(a);
-// }
+float32x4_t test_vrnd64zq_f32(float32x4_t a) {
+  return vrnd64zq_f32(a);
+
+  // CIR-LABEL: vrnd64zq_f32
+  // CIR: [[TMP0:%.*]] = cir.llvm.intrinsic "aarch64.neon.frint64z" {{.*}} : (!cir.vector<!cir.float x 4>) -> !cir.vector<!cir.float x 4>
+
+  // LLVM-LABEL: @test_vrnd64zq_f32
+  // LLVM:  [[RND:%.*]] =  call <4 x float> @llvm.aarch64.neon.frint64z.v4f32(<4 x float> %0)
+  // LLVM:  ret <4 x float> [[RND]]
+}
 
 float64x1_t test_vrnd32x_f64(float64x1_t a) {
   return vrnd32x_f64(a);
@@ -182,13 +196,27 @@ float64x2_t test_vrnd64xq_f64(float64x2_t a) {
 // CHECK-LABEL: test_vrnd64z_f64
 // CHECK:  [[RND:%.*]] =  call <1 x double> @llvm.aarch64.neon.frint64z.v1f64(<1 x double> %a)
 // CHECK:  ret <1 x double> [[RND]]
-// float64x1_t test_vrnd64z_f64(float64x1_t a) {
-//   return vrnd64z_f64(a);
-// }
+float64x1_t test_vrnd64z_f64(float64x1_t a) {
+  return vrnd64z_f64(a);
+
+  // CIR-LABEL: vrnd64z_f64
+  // CIR: [[TMP0:%.*]] = cir.llvm.intrinsic "aarch64.neon.frint64z" {{.*}} : (!cir.vector<!cir.double x 1>) -> !cir.vector<!cir.double x 1>
+
+  // LLVM-LABEL: @test_vrnd64z_f64
+  // LLVM:  [[RND:%.*]] =  call <1 x double> @llvm.aarch64.neon.frint64z.v1f64(<1 x double> %0)
+  // LLVM:  ret <1 x double> [[RND]]
+}
 
 // CHECK-LABEL: test_vrnd64zq_f64
 // CHECK:  [[RND:%.*]] =  call <2 x double> @llvm.aarch64.neon.frint64z.v2f64(<2 x double> %a)
 // CHECK:  ret <2 x double> [[RND]]
-// float64x2_t test_vrnd64zq_f64(float64x2_t a) {
-//   return vrnd64zq_f64(a);
-// }
+float64x2_t test_vrnd64zq_f64(float64x2_t a) {
+  return vrnd64zq_f64(a);
+
+  // CIR-LABEL: vrnd64zq_f64
+  // CIR: [[TMP0:%.*]] = cir.llvm.intrinsic "aarch64.neon.frint64z" {{.*}} : (!cir.vector<!cir.double x 2>) -> !cir.vector<!cir.double x 2>
+
+  // LLVM-LABEL: @test_vrnd64zq_f64
+  // LLVM:  [[RND:%.*]] =  call <2 x double> @llvm.aarch64.neon.frint64z.v2f64(<2 x double> %0)
+  // LLVM:  ret <2 x double> [[RND]]
+}