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[RISCV] Combine (xor (trunc (X cc Y)) 1) -> (trunc (X !cc Y)) for RV64LegalI32.
This is needed with RV64LegalI32 when the setcc is created after type legalization. An i1 xor would have been promoted to i32, but the setcc would have i64 result.
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2 files changed

+35
-36
lines changed

2 files changed

+35
-36
lines changed

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -12933,6 +12933,23 @@ static SDValue performXORCombine(SDNode *N, SelectionDAG &DAG,
1293312933
}
1293412934
}
1293512935

12936+
// Combine (xor (trunc (X cc Y)) 1) -> (trunc (X !cc Y)). This is needed with
12937+
// RV64LegalI32 when the setcc is created after type legalization. An i1 xor
12938+
// would have been promoted to i32, but the setcc would have i64 result.
12939+
if (N->getValueType(0) == MVT::i32 && N0.getOpcode() == ISD::TRUNCATE &&
12940+
isOneConstant(N1) && N0.getOperand(0).getOpcode() == ISD::SETCC) {
12941+
SDValue N00 = N0.getOperand(0);
12942+
SDLoc DL(N);
12943+
SDValue LHS = N00.getOperand(0);
12944+
SDValue RHS = N00.getOperand(1);
12945+
SDValue CC = N00.getOperand(2);
12946+
ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
12947+
LHS.getValueType());
12948+
SDValue Setcc = DAG.getSetCC(SDLoc(N00), N0.getOperand(0).getValueType(),
12949+
LHS, RHS, NotCC);
12950+
return DAG.getNode(ISD::TRUNCATE, SDLoc(N0), N->getValueType(0), Setcc);
12951+
}
12952+
1293612953
if (SDValue V = combineBinOpToReduce(N, DAG, Subtarget))
1293712954
return V;
1293812955
if (SDValue V = combineBinOpOfExtractToReduceTree(N, DAG, Subtarget))

‎llvm/test/CodeGen/RISCV/rv64-legal-i32/xaluo.ll

Lines changed: 18 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -997,26 +997,23 @@ define i1 @saddo.not.i32(i32 signext %v1, i32 signext %v2) {
997997
; RV64-NEXT: addw a2, a0, a1
998998
; RV64-NEXT: add a0, a0, a1
999999
; RV64-NEXT: xor a0, a0, a2
1000-
; RV64-NEXT: snez a0, a0
1001-
; RV64-NEXT: xori a0, a0, 1
1000+
; RV64-NEXT: seqz a0, a0
10021001
; RV64-NEXT: ret
10031002
;
10041003
; RV64ZBA-LABEL: saddo.not.i32:
10051004
; RV64ZBA: # %bb.0: # %entry
10061005
; RV64ZBA-NEXT: addw a2, a0, a1
10071006
; RV64ZBA-NEXT: add a0, a0, a1
10081007
; RV64ZBA-NEXT: xor a0, a0, a2
1009-
; RV64ZBA-NEXT: snez a0, a0
1010-
; RV64ZBA-NEXT: xori a0, a0, 1
1008+
; RV64ZBA-NEXT: seqz a0, a0
10111009
; RV64ZBA-NEXT: ret
10121010
;
10131011
; RV64ZICOND-LABEL: saddo.not.i32:
10141012
; RV64ZICOND: # %bb.0: # %entry
10151013
; RV64ZICOND-NEXT: addw a2, a0, a1
10161014
; RV64ZICOND-NEXT: add a0, a0, a1
10171015
; RV64ZICOND-NEXT: xor a0, a0, a2
1018-
; RV64ZICOND-NEXT: snez a0, a0
1019-
; RV64ZICOND-NEXT: xori a0, a0, 1
1016+
; RV64ZICOND-NEXT: seqz a0, a0
10201017
; RV64ZICOND-NEXT: ret
10211018
entry:
10221019
%t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
@@ -1266,26 +1263,23 @@ define i1 @ssubo.not.i32(i32 signext %v1, i32 signext %v2) {
12661263
; RV64-NEXT: subw a2, a0, a1
12671264
; RV64-NEXT: sub a0, a0, a1
12681265
; RV64-NEXT: xor a0, a0, a2
1269-
; RV64-NEXT: snez a0, a0
1270-
; RV64-NEXT: xori a0, a0, 1
1266+
; RV64-NEXT: seqz a0, a0
12711267
; RV64-NEXT: ret
12721268
;
12731269
; RV64ZBA-LABEL: ssubo.not.i32:
12741270
; RV64ZBA: # %bb.0: # %entry
12751271
; RV64ZBA-NEXT: subw a2, a0, a1
12761272
; RV64ZBA-NEXT: sub a0, a0, a1
12771273
; RV64ZBA-NEXT: xor a0, a0, a2
1278-
; RV64ZBA-NEXT: snez a0, a0
1279-
; RV64ZBA-NEXT: xori a0, a0, 1
1274+
; RV64ZBA-NEXT: seqz a0, a0
12801275
; RV64ZBA-NEXT: ret
12811276
;
12821277
; RV64ZICOND-LABEL: ssubo.not.i32:
12831278
; RV64ZICOND: # %bb.0: # %entry
12841279
; RV64ZICOND-NEXT: subw a2, a0, a1
12851280
; RV64ZICOND-NEXT: sub a0, a0, a1
12861281
; RV64ZICOND-NEXT: xor a0, a0, a2
1287-
; RV64ZICOND-NEXT: snez a0, a0
1288-
; RV64ZICOND-NEXT: xori a0, a0, 1
1282+
; RV64ZICOND-NEXT: seqz a0, a0
12891283
; RV64ZICOND-NEXT: ret
12901284
entry:
12911285
%t = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %v1, i32 %v2)
@@ -1535,26 +1529,23 @@ define i1 @smulo.not.i32(i32 signext %v1, i32 signext %v2) {
15351529
; RV64-NEXT: mulw a2, a0, a1
15361530
; RV64-NEXT: mul a0, a0, a1
15371531
; RV64-NEXT: xor a0, a0, a2
1538-
; RV64-NEXT: snez a0, a0
1539-
; RV64-NEXT: xori a0, a0, 1
1532+
; RV64-NEXT: seqz a0, a0
15401533
; RV64-NEXT: ret
15411534
;
15421535
; RV64ZBA-LABEL: smulo.not.i32:
15431536
; RV64ZBA: # %bb.0: # %entry
15441537
; RV64ZBA-NEXT: mulw a2, a0, a1
15451538
; RV64ZBA-NEXT: mul a0, a0, a1
15461539
; RV64ZBA-NEXT: xor a0, a0, a2
1547-
; RV64ZBA-NEXT: snez a0, a0
1548-
; RV64ZBA-NEXT: xori a0, a0, 1
1540+
; RV64ZBA-NEXT: seqz a0, a0
15491541
; RV64ZBA-NEXT: ret
15501542
;
15511543
; RV64ZICOND-LABEL: smulo.not.i32:
15521544
; RV64ZICOND: # %bb.0: # %entry
15531545
; RV64ZICOND-NEXT: mulw a2, a0, a1
15541546
; RV64ZICOND-NEXT: mul a0, a0, a1
15551547
; RV64ZICOND-NEXT: xor a0, a0, a2
1556-
; RV64ZICOND-NEXT: snez a0, a0
1557-
; RV64ZICOND-NEXT: xori a0, a0, 1
1548+
; RV64ZICOND-NEXT: seqz a0, a0
15581549
; RV64ZICOND-NEXT: ret
15591550
entry:
15601551
%t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2)
@@ -1610,8 +1601,7 @@ define i1 @smulo.not.i64(i64 %v1, i64 %v2) {
16101601
; RV64-NEXT: mul a0, a0, a1
16111602
; RV64-NEXT: srai a0, a0, 63
16121603
; RV64-NEXT: xor a0, a2, a0
1613-
; RV64-NEXT: snez a0, a0
1614-
; RV64-NEXT: xori a0, a0, 1
1604+
; RV64-NEXT: seqz a0, a0
16151605
; RV64-NEXT: ret
16161606
;
16171607
; RV64ZBA-LABEL: smulo.not.i64:
@@ -1620,8 +1610,7 @@ define i1 @smulo.not.i64(i64 %v1, i64 %v2) {
16201610
; RV64ZBA-NEXT: mul a0, a0, a1
16211611
; RV64ZBA-NEXT: srai a0, a0, 63
16221612
; RV64ZBA-NEXT: xor a0, a2, a0
1623-
; RV64ZBA-NEXT: snez a0, a0
1624-
; RV64ZBA-NEXT: xori a0, a0, 1
1613+
; RV64ZBA-NEXT: seqz a0, a0
16251614
; RV64ZBA-NEXT: ret
16261615
;
16271616
; RV64ZICOND-LABEL: smulo.not.i64:
@@ -1630,8 +1619,7 @@ define i1 @smulo.not.i64(i64 %v1, i64 %v2) {
16301619
; RV64ZICOND-NEXT: mul a0, a0, a1
16311620
; RV64ZICOND-NEXT: srai a0, a0, 63
16321621
; RV64ZICOND-NEXT: xor a0, a2, a0
1633-
; RV64ZICOND-NEXT: snez a0, a0
1634-
; RV64ZICOND-NEXT: xori a0, a0, 1
1622+
; RV64ZICOND-NEXT: seqz a0, a0
16351623
; RV64ZICOND-NEXT: ret
16361624
entry:
16371625
%t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %v1, i64 %v2)
@@ -1689,8 +1677,7 @@ define i1 @umulo.not.i32(i32 signext %v1, i32 signext %v2) {
16891677
; RV64-NEXT: slli a0, a0, 32
16901678
; RV64-NEXT: mulhu a0, a0, a1
16911679
; RV64-NEXT: srai a0, a0, 32
1692-
; RV64-NEXT: snez a0, a0
1693-
; RV64-NEXT: xori a0, a0, 1
1680+
; RV64-NEXT: seqz a0, a0
16941681
; RV64-NEXT: ret
16951682
;
16961683
; RV64ZBA-LABEL: umulo.not.i32:
@@ -1699,8 +1686,7 @@ define i1 @umulo.not.i32(i32 signext %v1, i32 signext %v2) {
16991686
; RV64ZBA-NEXT: zext.w a0, a0
17001687
; RV64ZBA-NEXT: mul a0, a0, a1
17011688
; RV64ZBA-NEXT: srai a0, a0, 32
1702-
; RV64ZBA-NEXT: snez a0, a0
1703-
; RV64ZBA-NEXT: xori a0, a0, 1
1689+
; RV64ZBA-NEXT: seqz a0, a0
17041690
; RV64ZBA-NEXT: ret
17051691
;
17061692
; RV64ZICOND-LABEL: umulo.not.i32:
@@ -1709,8 +1695,7 @@ define i1 @umulo.not.i32(i32 signext %v1, i32 signext %v2) {
17091695
; RV64ZICOND-NEXT: slli a0, a0, 32
17101696
; RV64ZICOND-NEXT: mulhu a0, a0, a1
17111697
; RV64ZICOND-NEXT: srai a0, a0, 32
1712-
; RV64ZICOND-NEXT: snez a0, a0
1713-
; RV64ZICOND-NEXT: xori a0, a0, 1
1698+
; RV64ZICOND-NEXT: seqz a0, a0
17141699
; RV64ZICOND-NEXT: ret
17151700
entry:
17161701
%t = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %v1, i32 %v2)
@@ -1756,22 +1741,19 @@ define i1 @umulo.not.i64(i64 %v1, i64 %v2) {
17561741
; RV64-LABEL: umulo.not.i64:
17571742
; RV64: # %bb.0: # %entry
17581743
; RV64-NEXT: mulhu a0, a0, a1
1759-
; RV64-NEXT: snez a0, a0
1760-
; RV64-NEXT: xori a0, a0, 1
1744+
; RV64-NEXT: seqz a0, a0
17611745
; RV64-NEXT: ret
17621746
;
17631747
; RV64ZBA-LABEL: umulo.not.i64:
17641748
; RV64ZBA: # %bb.0: # %entry
17651749
; RV64ZBA-NEXT: mulhu a0, a0, a1
1766-
; RV64ZBA-NEXT: snez a0, a0
1767-
; RV64ZBA-NEXT: xori a0, a0, 1
1750+
; RV64ZBA-NEXT: seqz a0, a0
17681751
; RV64ZBA-NEXT: ret
17691752
;
17701753
; RV64ZICOND-LABEL: umulo.not.i64:
17711754
; RV64ZICOND: # %bb.0: # %entry
17721755
; RV64ZICOND-NEXT: mulhu a0, a0, a1
1773-
; RV64ZICOND-NEXT: snez a0, a0
1774-
; RV64ZICOND-NEXT: xori a0, a0, 1
1756+
; RV64ZICOND-NEXT: seqz a0, a0
17751757
; RV64ZICOND-NEXT: ret
17761758
entry:
17771759
%t = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %v1, i64 %v2)

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