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[LV][EVL] Support fpext/fptrunc/fptosi/fptoui/sitofp/uitofp/inttoptr/ptrtoint of cast instruction with EVL-vectorization
1 parent a04e5ec commit 0b102ba

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3 files changed

+473
-7
lines changed

3 files changed

+473
-7
lines changed

llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp

+20-3
Original file line numberDiff line numberDiff line change
@@ -1384,15 +1384,32 @@ void VPWidenCastRecipe::execute(VPTransformState &State) {
13841384
}
13851385
}
13861386

1387+
static bool isCastInstruction(unsigned Opcode) {
1388+
switch (Opcode) {
1389+
case Instruction::SExt:
1390+
case Instruction::ZExt:
1391+
case Instruction::Trunc:
1392+
case Instruction::FPExt:
1393+
case Instruction::FPTrunc:
1394+
case Instruction::FPToSI:
1395+
case Instruction::FPToUI:
1396+
case Instruction::SIToFP:
1397+
case Instruction::UIToFP:
1398+
case Instruction::PtrToInt:
1399+
case Instruction::IntToPtr:
1400+
return true;
1401+
default:
1402+
return false;
1403+
}
1404+
}
1405+
13871406
void VPWidenCastEVLRecipe::execute(VPTransformState &State) {
13881407
unsigned Opcode = getOpcode();
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State.setDebugLocFrom(getDebugLoc());
13901409
assert(State.UF == 1 && "Expected only UF == 1 when vectorizing with "
13911410
"explicit vector length.");
13921411

1393-
// TODO: add more cast instruction, eg: fptoint/inttofp/inttoptr/fptofp
1394-
if (Opcode == Instruction::SExt || Opcode == Instruction::ZExt ||
1395-
Opcode == Instruction::Trunc) {
1412+
if (isCastInstruction(Opcode)) {
13961413
Value *SrcVal = State.get(getOperand(0), 0);
13971414
VectorType *DsType = VectorType::get(getResultType(), State.VF);
13981415

llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp

+20-3
Original file line numberDiff line numberDiff line change
@@ -1314,6 +1314,25 @@ void VPlanTransforms::addActiveLaneMask(
13141314
HeaderMask->replaceAllUsesWith(LaneMask);
13151315
}
13161316

1317+
static bool isCastInstruction(unsigned Opcode) {
1318+
switch (Opcode) {
1319+
case Instruction::SExt:
1320+
case Instruction::ZExt:
1321+
case Instruction::Trunc:
1322+
case Instruction::FPExt:
1323+
case Instruction::FPTrunc:
1324+
case Instruction::FPToSI:
1325+
case Instruction::FPToUI:
1326+
case Instruction::SIToFP:
1327+
case Instruction::UIToFP:
1328+
case Instruction::PtrToInt:
1329+
case Instruction::IntToPtr:
1330+
return true;
1331+
default:
1332+
return false;
1333+
}
1334+
}
1335+
13171336
/// Replace recipes with their EVL variants.
13181337
static void transformRecipestoEVLRecipes(VPlan &Plan, VPValue &EVL) {
13191338
SmallVector<VPValue *> HeaderMasks = collectAllHeaderMasks(Plan);
@@ -1347,9 +1366,7 @@ static void transformRecipestoEVLRecipes(VPlan &Plan, VPValue &EVL) {
13471366
.Case<VPWidenCastRecipe>(
13481367
[&](VPWidenCastRecipe *W) -> VPRecipeBase * {
13491368
unsigned Opcode = W->getOpcode();
1350-
if (Opcode != Instruction::SExt &&
1351-
Opcode != Instruction::ZExt &&
1352-
Opcode != Instruction::Trunc)
1369+
if (!isCastInstruction(Opcode))
13531370
return nullptr;
13541371
return new VPWidenCastEVLRecipe(*W, EVL);
13551372
})

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