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vitalybukavitalybuka
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[𝘀𝗽𝗿] initial version
Created using spr 1.3.4
2 parents 1b66306 + 90e450b commit 158fadb

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‎libcxx/test/std/time/time.zone/time.zone.timezone/time.zone.members/get_info.local_time.pass.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5,14 +5,14 @@
55
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
66
//
77
//===----------------------------------------------------------------------===//
8+
//
9+
// REQUIRES: long_tests
810

911
// UNSUPPORTED: c++03, c++11, c++14, c++17
1012
// UNSUPPORTED: no-filesystem, no-localization, no-tzdb
1113

1214
// XFAIL: libcpp-has-no-experimental-tzdb
1315
// XFAIL: availability-tzdb-missing
14-
// Times out under HWASan
15-
// UNSUPPORTED: hwasan
1616

1717
// <chrono>
1818

‎llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp

Lines changed: 116 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3289,6 +3289,106 @@ struct MemorySanitizerVisitor : public InstVisitor<MemorySanitizerVisitor> {
32893289
setOriginForNaryOp(I);
32903290
}
32913291

3292+
// Convert `Mask` into `<n x i1>`.
3293+
Constant *createDppMask(unsigned Width, unsigned Mask) {
3294+
SmallVector<Constant *, 4> R(Width);
3295+
for (auto &M : R) {
3296+
M = ConstantInt::getBool(F.getContext(), Mask & 1);
3297+
Mask >>= 1;
3298+
}
3299+
return ConstantVector::get(R);
3300+
}
3301+
3302+
// Calculate output shadow as array of booleans `<n x i1>`, assuming if any
3303+
// arg is poisoned, entire dot product is poisoned.
3304+
Value *findDppPoisonedOutput(IRBuilder<> &IRB, Value *S, unsigned SrcMask,
3305+
unsigned DstMask) {
3306+
const unsigned Width =
3307+
cast<FixedVectorType>(S->getType())->getNumElements();
3308+
3309+
S = IRB.CreateSelect(createDppMask(Width, SrcMask), S,
3310+
Constant::getNullValue(S->getType()));
3311+
Value *SElem = IRB.CreateOrReduce(S);
3312+
Value *IsClean = IRB.CreateIsNull(SElem, "_msdpp");
3313+
Value *DstMaskV = createDppMask(Width, DstMask);
3314+
3315+
return IRB.CreateSelect(
3316+
IsClean, Constant::getNullValue(DstMaskV->getType()), DstMaskV);
3317+
}
3318+
3319+
// See `Intel Intrinsics Guide` for `_dp_p*` instructions.
3320+
//
3321+
// 2 and 4 element versions produce single scalar of dot product, and then
3322+
// puts it into elements of output vector, selected by 4 lowest bits of the
3323+
// mask. Top 4 bits of the mask control which elements of input to use for dot
3324+
// product.
3325+
//
3326+
// 8 element version mask still has only 4 bit for input, and 4 bit for output
3327+
// mask. According to the spec it just operates as 4 element version on first
3328+
// 4 elements of inputs and output, and then on last 4 elements of inputs and
3329+
// output.
3330+
void handleDppIntrinsic(IntrinsicInst &I) {
3331+
IRBuilder<> IRB(&I);
3332+
3333+
Value *S0 = getShadow(&I, 0);
3334+
Value *S1 = getShadow(&I, 1);
3335+
Value *S = IRB.CreateOr(S0, S1);
3336+
3337+
const unsigned Width =
3338+
cast<FixedVectorType>(S->getType())->getNumElements();
3339+
assert(Width == 2 || Width == 4 || Width == 8);
3340+
3341+
const unsigned Mask = cast<ConstantInt>(I.getArgOperand(2))->getZExtValue();
3342+
const unsigned SrcMask = Mask >> 4;
3343+
const unsigned DstMask = Mask & 0xf;
3344+
3345+
// Calculate shadow as `<n x i1>`.
3346+
Value *SI1 = findDppPoisonedOutput(IRB, S, SrcMask, DstMask);
3347+
if (Width == 8) {
3348+
// First 4 elements of shadow are already calculated. `makeDppShadow`
3349+
// operats on 32 bit masks, so we can just shift masks, and repeat.
3350+
SI1 = IRB.CreateOr(
3351+
SI1, findDppPoisonedOutput(IRB, S, SrcMask << 4, DstMask << 4));
3352+
}
3353+
// Extend to real size of shadow, poisoning either all or none bits of an
3354+
// element.
3355+
S = IRB.CreateSExt(SI1, S->getType(), "_msdpp");
3356+
3357+
setShadow(&I, S);
3358+
setOriginForNaryOp(I);
3359+
}
3360+
3361+
Value *convertBlendvToSelectMask(IRBuilder<> &IRB, Value *C) {
3362+
C = CreateAppToShadowCast(IRB, C);
3363+
FixedVectorType *FVT = cast<FixedVectorType>(C->getType());
3364+
unsigned ElSize = FVT->getElementType()->getPrimitiveSizeInBits();
3365+
C = IRB.CreateAShr(C, ElSize - 1);
3366+
FVT = FixedVectorType::get(IRB.getInt1Ty(), FVT->getNumElements());
3367+
return IRB.CreateTrunc(C, FVT);
3368+
}
3369+
3370+
// `blendv(f, t, c)` is effectively `select(c[top_bit], t, f)`.
3371+
void handleBlendvIntrinsic(IntrinsicInst &I) {
3372+
Value *C = I.getOperand(2);
3373+
Value *T = I.getOperand(1);
3374+
Value *F = I.getOperand(0);
3375+
3376+
Value *Sc = getShadow(&I, 2);
3377+
Value *Oc = MS.TrackOrigins ? getOrigin(C) : nullptr;
3378+
3379+
{
3380+
IRBuilder<> IRB(&I);
3381+
// Extract top bit from condition and its shadow.
3382+
C = convertBlendvToSelectMask(IRB, C);
3383+
Sc = convertBlendvToSelectMask(IRB, Sc);
3384+
3385+
setShadow(C, Sc);
3386+
setOrigin(C, Oc);
3387+
}
3388+
3389+
handleSelectLikeInst(I, C, T, F);
3390+
}
3391+
32923392
// Instrument sum-of-absolute-differences intrinsic.
32933393
void handleVectorSadIntrinsic(IntrinsicInst &I) {
32943394
const unsigned SignificantBitsPerResultElement = 16;
@@ -3644,7 +3744,7 @@ struct MemorySanitizerVisitor : public InstVisitor<MemorySanitizerVisitor> {
36443744
setOriginForNaryOp(I);
36453745
}
36463746

3647-
SmallVector<int, 8> getPclmulMask(unsigned Width, bool OddElements) {
3747+
static SmallVector<int, 8> getPclmulMask(unsigned Width, bool OddElements) {
36483748
SmallVector<int, 8> Mask;
36493749
for (unsigned X = OddElements ? 1 : 0; X < Width; X += 2) {
36503750
Mask.append(2, X);
@@ -3960,6 +4060,21 @@ struct MemorySanitizerVisitor : public InstVisitor<MemorySanitizerVisitor> {
39604060
handleVectorPackIntrinsic(I);
39614061
break;
39624062

4063+
case Intrinsic::x86_sse41_pblendvb:
4064+
case Intrinsic::x86_sse41_blendvpd:
4065+
case Intrinsic::x86_sse41_blendvps:
4066+
case Intrinsic::x86_avx_blendv_pd_256:
4067+
case Intrinsic::x86_avx_blendv_ps_256:
4068+
case Intrinsic::x86_avx2_pblendvb:
4069+
handleBlendvIntrinsic(I);
4070+
break;
4071+
4072+
case Intrinsic::x86_avx_dp_ps_256:
4073+
case Intrinsic::x86_sse41_dppd:
4074+
case Intrinsic::x86_sse41_dpps:
4075+
handleDppIntrinsic(I);
4076+
break;
4077+
39634078
case Intrinsic::x86_mmx_packsswb:
39644079
case Intrinsic::x86_mmx_packuswb:
39654080
handleVectorPackIntrinsic(I, 16);

‎llvm/test/Instrumentation/MemorySanitizer/X86/avx-intrinsics-x86.ll

Lines changed: 44 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -38,14 +38,24 @@ declare <8 x float> @llvm.x86.avx.addsub.ps.256(<8 x float>, <8 x float>) nounwi
3838

3939
define <4 x double> @test_x86_avx_blendv_pd_256(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2) #0 {
4040
; CHECK-LABEL: @test_x86_avx_blendv_pd_256(
41-
; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 8
41+
; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 64) to ptr), align 8
4242
; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8
43-
; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 64) to ptr), align 8
43+
; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 8
4444
; CHECK-NEXT: call void @llvm.donothing()
45-
; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i64> [[TMP1]], [[TMP2]]
46-
; CHECK-NEXT: [[_MSPROP1:%.*]] = or <4 x i64> [[_MSPROP]], [[TMP3]]
47-
; CHECK-NEXT: [[RES:%.*]] = call <4 x double> @llvm.x86.avx.blendv.pd.256(<4 x double> [[A0:%.*]], <4 x double> [[A1:%.*]], <4 x double> [[A2:%.*]])
48-
; CHECK-NEXT: store <4 x i64> [[_MSPROP1]], ptr @__msan_retval_tls, align 8
45+
; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x double> [[A2:%.*]] to <4 x i64>
46+
; CHECK-NEXT: [[TMP5:%.*]] = ashr <4 x i64> [[TMP4]], <i64 63, i64 63, i64 63, i64 63>
47+
; CHECK-NEXT: [[TMP6:%.*]] = trunc <4 x i64> [[TMP5]] to <4 x i1>
48+
; CHECK-NEXT: [[TMP7:%.*]] = ashr <4 x i64> [[TMP1]], <i64 63, i64 63, i64 63, i64 63>
49+
; CHECK-NEXT: [[TMP8:%.*]] = trunc <4 x i64> [[TMP7]] to <4 x i1>
50+
; CHECK-NEXT: [[TMP9:%.*]] = select <4 x i1> [[TMP6]], <4 x i64> [[TMP2]], <4 x i64> [[TMP3]]
51+
; CHECK-NEXT: [[TMP10:%.*]] = bitcast <4 x double> [[A1:%.*]] to <4 x i64>
52+
; CHECK-NEXT: [[TMP11:%.*]] = bitcast <4 x double> [[A0:%.*]] to <4 x i64>
53+
; CHECK-NEXT: [[TMP12:%.*]] = xor <4 x i64> [[TMP10]], [[TMP11]]
54+
; CHECK-NEXT: [[TMP13:%.*]] = or <4 x i64> [[TMP12]], [[TMP2]]
55+
; CHECK-NEXT: [[TMP14:%.*]] = or <4 x i64> [[TMP13]], [[TMP3]]
56+
; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <4 x i1> [[TMP8]], <4 x i64> [[TMP14]], <4 x i64> [[TMP9]]
57+
; CHECK-NEXT: [[RES:%.*]] = call <4 x double> @llvm.x86.avx.blendv.pd.256(<4 x double> [[A0]], <4 x double> [[A1]], <4 x double> [[A2]])
58+
; CHECK-NEXT: store <4 x i64> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 8
4959
; CHECK-NEXT: ret <4 x double> [[RES]]
5060
;
5161
%res = call <4 x double> @llvm.x86.avx.blendv.pd.256(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2) ; <<4 x double>> [#uses=1]
@@ -56,14 +66,24 @@ declare <4 x double> @llvm.x86.avx.blendv.pd.256(<4 x double>, <4 x double>, <4
5666

5767
define <8 x float> @test_x86_avx_blendv_ps_256(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2) #0 {
5868
; CHECK-LABEL: @test_x86_avx_blendv_ps_256(
59-
; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8
69+
; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 64) to ptr), align 8
6070
; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8
61-
; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 64) to ptr), align 8
71+
; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8
6272
; CHECK-NEXT: call void @llvm.donothing()
63-
; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i32> [[TMP1]], [[TMP2]]
64-
; CHECK-NEXT: [[_MSPROP1:%.*]] = or <8 x i32> [[_MSPROP]], [[TMP3]]
65-
; CHECK-NEXT: [[RES:%.*]] = call <8 x float> @llvm.x86.avx.blendv.ps.256(<8 x float> [[A0:%.*]], <8 x float> [[A1:%.*]], <8 x float> [[A2:%.*]])
66-
; CHECK-NEXT: store <8 x i32> [[_MSPROP1]], ptr @__msan_retval_tls, align 8
73+
; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x float> [[A2:%.*]] to <8 x i32>
74+
; CHECK-NEXT: [[TMP5:%.*]] = ashr <8 x i32> [[TMP4]], <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>
75+
; CHECK-NEXT: [[TMP6:%.*]] = trunc <8 x i32> [[TMP5]] to <8 x i1>
76+
; CHECK-NEXT: [[TMP7:%.*]] = ashr <8 x i32> [[TMP1]], <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>
77+
; CHECK-NEXT: [[TMP8:%.*]] = trunc <8 x i32> [[TMP7]] to <8 x i1>
78+
; CHECK-NEXT: [[TMP9:%.*]] = select <8 x i1> [[TMP6]], <8 x i32> [[TMP2]], <8 x i32> [[TMP3]]
79+
; CHECK-NEXT: [[TMP10:%.*]] = bitcast <8 x float> [[A1:%.*]] to <8 x i32>
80+
; CHECK-NEXT: [[TMP11:%.*]] = bitcast <8 x float> [[A0:%.*]] to <8 x i32>
81+
; CHECK-NEXT: [[TMP12:%.*]] = xor <8 x i32> [[TMP10]], [[TMP11]]
82+
; CHECK-NEXT: [[TMP13:%.*]] = or <8 x i32> [[TMP12]], [[TMP2]]
83+
; CHECK-NEXT: [[TMP14:%.*]] = or <8 x i32> [[TMP13]], [[TMP3]]
84+
; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP8]], <8 x i32> [[TMP14]], <8 x i32> [[TMP9]]
85+
; CHECK-NEXT: [[RES:%.*]] = call <8 x float> @llvm.x86.avx.blendv.ps.256(<8 x float> [[A0]], <8 x float> [[A1]], <8 x float> [[A2]])
86+
; CHECK-NEXT: store <8 x i32> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 8
6787
; CHECK-NEXT: ret <8 x float> [[RES]]
6888
;
6989
%res = call <8 x float> @llvm.x86.avx.blendv.ps.256(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2) ; <<8 x float>> [#uses=1]
@@ -389,18 +409,19 @@ define <8 x float> @test_x86_avx_dp_ps_256(<8 x float> %a0, <8 x float> %a1) #0
389409
; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8
390410
; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8
391411
; CHECK-NEXT: call void @llvm.donothing()
392-
; CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i32> [[TMP1]] to i256
393-
; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP3]], 0
394-
; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i32> [[TMP2]] to i256
395-
; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP4]], 0
396-
; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]
397-
; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF0]]
398-
; CHECK: 5:
399-
; CHECK-NEXT: call void @__msan_warning_noreturn()
400-
; CHECK-NEXT: unreachable
401-
; CHECK: 6:
412+
; CHECK-NEXT: [[TMP3:%.*]] = or <8 x i32> [[TMP1]], [[TMP2]]
413+
; CHECK-NEXT: [[TMP4:%.*]] = select <8 x i1> <i1 false, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false>, <8 x i32> [[TMP3]], <8 x i32> zeroinitializer
414+
; CHECK-NEXT: [[TMP5:%.*]] = call i32 @llvm.vector.reduce.or.v8i32(<8 x i32> [[TMP4]])
415+
; CHECK-NEXT: [[_MSDPP:%.*]] = icmp eq i32 [[TMP5]], 0
416+
; CHECK-NEXT: [[TMP6:%.*]] = select i1 [[_MSDPP]], <8 x i1> zeroinitializer, <8 x i1> <i1 false, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false>
417+
; CHECK-NEXT: [[TMP7:%.*]] = select <8 x i1> <i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true>, <8 x i32> [[TMP3]], <8 x i32> zeroinitializer
418+
; CHECK-NEXT: [[TMP8:%.*]] = call i32 @llvm.vector.reduce.or.v8i32(<8 x i32> [[TMP7]])
419+
; CHECK-NEXT: [[_MSDPP1:%.*]] = icmp eq i32 [[TMP8]], 0
420+
; CHECK-NEXT: [[TMP9:%.*]] = select i1 [[_MSDPP1]], <8 x i1> zeroinitializer, <8 x i1> <i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true>
421+
; CHECK-NEXT: [[TMP10:%.*]] = or <8 x i1> [[TMP6]], [[TMP9]]
422+
; CHECK-NEXT: [[_MSDPP2:%.*]] = sext <8 x i1> [[TMP10]] to <8 x i32>
402423
; CHECK-NEXT: [[RES:%.*]] = call <8 x float> @llvm.x86.avx.dp.ps.256(<8 x float> [[A0:%.*]], <8 x float> [[A1:%.*]], i8 -18)
403-
; CHECK-NEXT: store <8 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8
424+
; CHECK-NEXT: store <8 x i32> [[_MSDPP2]], ptr @__msan_retval_tls, align 8
404425
; CHECK-NEXT: ret <8 x float> [[RES]]
405426
;
406427
%res = call <8 x float> @llvm.x86.avx.dp.ps.256(<8 x float> %a0, <8 x float> %a1, i8 -18) ; <<8 x float>> [#uses=1]

‎llvm/test/Instrumentation/MemorySanitizer/X86/avx2-intrinsics-x86.ll

Lines changed: 19 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -816,8 +816,8 @@ define <16 x i16> @test_x86_avx2_mpsadbw_load_op0(ptr %ptr, <32 x i8> %a1) #0 {
816816
; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8
817817
; CHECK-NEXT: [[TMP2:%.*]] = load <32 x i8>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
818818
; CHECK-NEXT: call void @llvm.donothing()
819-
; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP1]], 0
820-
; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]]
819+
; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0
820+
; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]]
821821
; CHECK: 3:
822822
; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]
823823
; CHECK-NEXT: unreachable
@@ -828,10 +828,10 @@ define <16 x i16> @test_x86_avx2_mpsadbw_load_op0(ptr %ptr, <32 x i8> %a1) #0 {
828828
; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr
829829
; CHECK-NEXT: [[_MSLD:%.*]] = load <32 x i8>, ptr [[TMP7]], align 32
830830
; CHECK-NEXT: [[TMP8:%.*]] = bitcast <32 x i8> [[_MSLD]] to i256
831-
; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP8]], 0
831+
; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP8]], 0
832832
; CHECK-NEXT: [[TMP9:%.*]] = bitcast <32 x i8> [[TMP2]] to i256
833-
; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i256 [[TMP9]], 0
834-
; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]
833+
; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i256 [[TMP9]], 0
834+
; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP1]], [[_MSCMP2]]
835835
; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP10:%.*]], label [[TMP11:%.*]], !prof [[PROF0]]
836836
; CHECK: 10:
837837
; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]]
@@ -881,14 +881,21 @@ define <16 x i16> @test_x86_avx2_packusdw_fold() #0 {
881881

882882
define <32 x i8> @test_x86_avx2_pblendvb(<32 x i8> %a0, <32 x i8> %a1, <32 x i8> %a2) #0 {
883883
; CHECK-LABEL: @test_x86_avx2_pblendvb(
884-
; CHECK-NEXT: [[TMP1:%.*]] = load <32 x i8>, ptr @__msan_param_tls, align 8
884+
; CHECK-NEXT: [[TMP1:%.*]] = load <32 x i8>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 64) to ptr), align 8
885885
; CHECK-NEXT: [[TMP2:%.*]] = load <32 x i8>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8
886-
; CHECK-NEXT: [[TMP3:%.*]] = load <32 x i8>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 64) to ptr), align 8
887-
; CHECK-NEXT: call void @llvm.donothing()
888-
; CHECK-NEXT: [[_MSPROP:%.*]] = or <32 x i8> [[TMP1]], [[TMP2]]
889-
; CHECK-NEXT: [[_MSPROP1:%.*]] = or <32 x i8> [[_MSPROP]], [[TMP3]]
890-
; CHECK-NEXT: [[RES:%.*]] = call <32 x i8> @llvm.x86.avx2.pblendvb(<32 x i8> [[A0:%.*]], <32 x i8> [[A1:%.*]], <32 x i8> [[A2:%.*]])
891-
; CHECK-NEXT: store <32 x i8> [[_MSPROP1]], ptr @__msan_retval_tls, align 8
886+
; CHECK-NEXT: [[TMP3:%.*]] = load <32 x i8>, ptr @__msan_param_tls, align 8
887+
; CHECK-NEXT: call void @llvm.donothing()
888+
; CHECK-NEXT: [[TMP4:%.*]] = ashr <32 x i8> [[A2:%.*]], <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
889+
; CHECK-NEXT: [[TMP5:%.*]] = trunc <32 x i8> [[TMP4]] to <32 x i1>
890+
; CHECK-NEXT: [[TMP6:%.*]] = ashr <32 x i8> [[TMP1]], <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
891+
; CHECK-NEXT: [[TMP7:%.*]] = trunc <32 x i8> [[TMP6]] to <32 x i1>
892+
; CHECK-NEXT: [[TMP8:%.*]] = select <32 x i1> [[TMP5]], <32 x i8> [[TMP2]], <32 x i8> [[TMP3]]
893+
; CHECK-NEXT: [[TMP9:%.*]] = xor <32 x i8> [[A1:%.*]], [[A0:%.*]]
894+
; CHECK-NEXT: [[TMP10:%.*]] = or <32 x i8> [[TMP9]], [[TMP2]]
895+
; CHECK-NEXT: [[TMP11:%.*]] = or <32 x i8> [[TMP10]], [[TMP3]]
896+
; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <32 x i1> [[TMP7]], <32 x i8> [[TMP11]], <32 x i8> [[TMP8]]
897+
; CHECK-NEXT: [[RES:%.*]] = call <32 x i8> @llvm.x86.avx2.pblendvb(<32 x i8> [[A0]], <32 x i8> [[A1]], <32 x i8> [[A2]])
898+
; CHECK-NEXT: store <32 x i8> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 8
892899
; CHECK-NEXT: ret <32 x i8> [[RES]]
893900
;
894901
%res = call <32 x i8> @llvm.x86.avx2.pblendvb(<32 x i8> %a0, <32 x i8> %a1, <32 x i8> %a2) ; <<32 x i8>> [#uses=1]

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