Skip to content

Commit 19da024

Browse files
committed
[LICM] Address comments
* Simplify test Transforms/LICM/hoist-binop.ll * Create new instructions instead of modifying in-place * Replacing isa + dyn_cast with single dyn_cast * Early exit * Add test for single use case
1 parent 64d318c commit 19da024

File tree

5 files changed

+124
-106
lines changed

5 files changed

+124
-106
lines changed

llvm/lib/Transforms/Scalar/LICM.cpp

Lines changed: 26 additions & 41 deletions
Original file line numberDiff line numberDiff line change
@@ -2796,55 +2796,40 @@ static bool hoistBOAssociation(Instruction &I, Loop &L,
27962796
ICFLoopSafetyInfo &SafetyInfo,
27972797
MemorySSAUpdater &MSSAU, AssumptionCache *AC,
27982798
DominatorTree *DT) {
2799-
if (!isa<BinaryOperator>(I))
2799+
BinaryOperator *BO = dyn_cast<BinaryOperator>(&I);
2800+
if (!BO || !BO->isAssociative())
28002801
return false;
28012802

2802-
Instruction::BinaryOps Opcode = dyn_cast<BinaryOperator>(&I)->getOpcode();
2803-
BinaryOperator *Op0 = dyn_cast<BinaryOperator>(I.getOperand(0));
2803+
Instruction::BinaryOps Opcode = BO->getOpcode();
2804+
BinaryOperator *Op0 = dyn_cast<BinaryOperator>(BO->getOperand(0));
28042805

2805-
auto ClearSubclassDataAfterReassociation = [](Instruction &I) {
2806-
FPMathOperator *FPMO = dyn_cast<FPMathOperator>(&I);
2807-
if (!FPMO) {
2808-
I.clearSubclassOptionalData();
2809-
return;
2810-
}
2811-
2812-
FastMathFlags FMF = I.getFastMathFlags();
2813-
I.clearSubclassOptionalData();
2814-
I.setFastMathFlags(FMF);
2815-
};
2816-
2817-
if (I.isAssociative()) {
2818-
// Transform: "(LV op C1) op C2" ==> "LV op (C1 op C2)"
2819-
if (Op0 && Op0->getOpcode() == Opcode) {
2820-
Value *LV = Op0->getOperand(0);
2821-
Value *C1 = Op0->getOperand(1);
2822-
Value *C2 = I.getOperand(1);
2806+
// Transform: "(LV op C1) op C2" ==> "LV op (C1 op C2)"
2807+
if (Op0 && Op0->getOpcode() == Opcode) {
2808+
Value *LV = Op0->getOperand(0);
2809+
Value *C1 = Op0->getOperand(1);
2810+
Value *C2 = BO->getOperand(1);
28232811

2824-
if (L.isLoopInvariant(LV) || !L.isLoopInvariant(C1) ||
2825-
!L.isLoopInvariant(C2))
2826-
return false;
2827-
2828-
bool singleUseOp0 = Op0->hasOneUse();
2812+
if (L.isLoopInvariant(LV) || !L.isLoopInvariant(C1) ||
2813+
!L.isLoopInvariant(C2))
2814+
return false;
28292815

2830-
// Conservatively clear all optional flags since they may not be
2831-
// preserved by the reassociation, but preserve fast-math flags where
2832-
// applicable,
2833-
ClearSubclassDataAfterReassociation(I);
2816+
auto *Preheader = L.getLoopPreheader();
2817+
assert(Preheader && "Loop is not in simplify form?");
2818+
IRBuilder<> Builder(Preheader->getTerminator());
2819+
Value *Inv = Builder.CreateBinOp(Opcode, C1, C2, "invariant.op");
28342820

2835-
auto *Preheader = L.getLoopPreheader();
2836-
assert(Preheader && "Loop is not in simplify form?");
2837-
IRBuilder<> Builder(Preheader->getTerminator());
2838-
Value *V = Builder.CreateBinOp(Opcode, C1, C2, "invariant.op");
2839-
I.setOperand(0, LV);
2840-
I.setOperand(1, V);
2821+
auto *NewBO = BinaryOperator::Create(Opcode, LV, Inv,
2822+
BO->getName() + ".reass", BO);
2823+
NewBO->copyIRFlags(BO);
2824+
BO->replaceAllUsesWith(NewBO);
2825+
eraseInstruction(*BO, SafetyInfo, MSSAU);
28412826

2842-
// Note: (LV op CV1) might not be erased if it has more than one use.
2843-
if (singleUseOp0)
2844-
eraseInstruction(cast<Instruction>(*Op0), SafetyInfo, MSSAU);
2827+
// Note: (LV op C1) might not be erased if it has more uses than the one we
2828+
// just replaced.
2829+
if (Op0->use_empty())
2830+
eraseInstruction(*Op0, SafetyInfo, MSSAU);
28452831

2846-
return true;
2847-
}
2832+
return true;
28482833
}
28492834

28502835
return false;

llvm/test/CodeGen/PowerPC/common-chain.ll

Lines changed: 24 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -785,7 +785,7 @@ define signext i32 @spill_reduce_succ(ptr %input1, ptr %input2, ptr %output, i64
785785
; CHECK-NEXT: add r15, r5, r11
786786
; CHECK-NEXT: sldi r11, r14, 3
787787
; CHECK-NEXT: add r29, r5, r29
788-
; CHECK-NEXT: add r28, r5, r26
788+
; CHECK-NEXT: add r28, r3, r26
789789
; CHECK-NEXT: add r19, r5, r19
790790
; CHECK-NEXT: add r21, r23, r9
791791
; CHECK-NEXT: add r24, r23, r8
@@ -794,21 +794,21 @@ define signext i32 @spill_reduce_succ(ptr %input1, ptr %input2, ptr %output, i64
794794
; CHECK-NEXT: add r25, r23, r20
795795
; CHECK-NEXT: add r20, r18, r20
796796
; CHECK-NEXT: add r30, r5, r30
797-
; CHECK-NEXT: add r18, r5, r16
797+
; CHECK-NEXT: add r18, r3, r16
798798
; CHECK-NEXT: add r24, r5, r24
799-
; CHECK-NEXT: add r23, r5, r21
799+
; CHECK-NEXT: add r23, r3, r21
800800
; CHECK-NEXT: add r27, r4, r26
801801
; CHECK-NEXT: add r22, r4, r21
802802
; CHECK-NEXT: add r17, r4, r16
803803
; CHECK-NEXT: add r2, r4, r11
804804
; CHECK-NEXT: rldicl r4, r7, 2, 1
805805
; CHECK-NEXT: sub r7, r8, r9
806806
; CHECK-NEXT: ld r8, -200(r1) # 8-byte Folded Reload
807-
; CHECK-NEXT: add r26, r3, r26
807+
; CHECK-NEXT: add r26, r5, r26
808808
; CHECK-NEXT: add r25, r5, r25
809-
; CHECK-NEXT: add r21, r3, r21
809+
; CHECK-NEXT: add r21, r5, r21
810810
; CHECK-NEXT: add r20, r5, r20
811-
; CHECK-NEXT: add r16, r3, r16
811+
; CHECK-NEXT: add r16, r5, r16
812812
; CHECK-NEXT: add r31, r5, r11
813813
; CHECK-NEXT: add r11, r3, r11
814814
; CHECK-NEXT: addi r4, r4, -4
@@ -842,61 +842,61 @@ define signext i32 @spill_reduce_succ(ptr %input1, ptr %input2, ptr %output, i64
842842
; CHECK-NEXT: lfdx f1, r15, r9
843843
; CHECK-NEXT: xsadddp f0, f1, f0
844844
; CHECK-NEXT: stfdx f0, r15, r9
845-
; CHECK-NEXT: lfd f0, 0(r16)
845+
; CHECK-NEXT: lfd f0, 0(r18)
846846
; CHECK-NEXT: lfd f1, 0(r17)
847847
; CHECK-NEXT: xsmuldp f0, f0, f1
848-
; CHECK-NEXT: lfdx f1, r18, r9
848+
; CHECK-NEXT: lfdx f1, r16, r9
849849
; CHECK-NEXT: xsadddp f0, f1, f0
850-
; CHECK-NEXT: stfdx f0, r18, r9
851-
; CHECK-NEXT: lfdx f0, r16, r7
850+
; CHECK-NEXT: stfdx f0, r16, r9
851+
; CHECK-NEXT: lfdx f0, r18, r7
852852
; CHECK-NEXT: lfdx f1, r17, r7
853853
; CHECK-NEXT: xsmuldp f0, f0, f1
854854
; CHECK-NEXT: lfdx f1, r19, r9
855855
; CHECK-NEXT: xsadddp f0, f1, f0
856856
; CHECK-NEXT: stfdx f0, r19, r9
857-
; CHECK-NEXT: lfdx f0, r16, r8
857+
; CHECK-NEXT: lfdx f0, r18, r8
858858
; CHECK-NEXT: lfdx f1, r17, r8
859-
; CHECK-NEXT: add r16, r16, r12
859+
; CHECK-NEXT: add r18, r18, r12
860860
; CHECK-NEXT: add r17, r17, r12
861861
; CHECK-NEXT: xsmuldp f0, f0, f1
862862
; CHECK-NEXT: lfdx f1, r20, r9
863863
; CHECK-NEXT: xsadddp f0, f1, f0
864864
; CHECK-NEXT: stfdx f0, r20, r9
865-
; CHECK-NEXT: lfd f0, 0(r21)
865+
; CHECK-NEXT: lfd f0, 0(r23)
866866
; CHECK-NEXT: lfd f1, 0(r22)
867867
; CHECK-NEXT: xsmuldp f0, f0, f1
868-
; CHECK-NEXT: lfdx f1, r23, r9
868+
; CHECK-NEXT: lfdx f1, r21, r9
869869
; CHECK-NEXT: xsadddp f0, f1, f0
870-
; CHECK-NEXT: stfdx f0, r23, r9
871-
; CHECK-NEXT: lfdx f0, r21, r7
870+
; CHECK-NEXT: stfdx f0, r21, r9
871+
; CHECK-NEXT: lfdx f0, r23, r7
872872
; CHECK-NEXT: lfdx f1, r22, r7
873873
; CHECK-NEXT: xsmuldp f0, f0, f1
874874
; CHECK-NEXT: lfdx f1, r24, r9
875875
; CHECK-NEXT: xsadddp f0, f1, f0
876876
; CHECK-NEXT: stfdx f0, r24, r9
877-
; CHECK-NEXT: lfdx f0, r21, r8
877+
; CHECK-NEXT: lfdx f0, r23, r8
878878
; CHECK-NEXT: lfdx f1, r22, r8
879-
; CHECK-NEXT: add r21, r21, r12
879+
; CHECK-NEXT: add r23, r23, r12
880880
; CHECK-NEXT: add r22, r22, r12
881881
; CHECK-NEXT: xsmuldp f0, f0, f1
882882
; CHECK-NEXT: lfdx f1, r25, r9
883883
; CHECK-NEXT: xsadddp f0, f1, f0
884884
; CHECK-NEXT: stfdx f0, r25, r9
885-
; CHECK-NEXT: lfd f0, 0(r26)
885+
; CHECK-NEXT: lfd f0, 0(r28)
886886
; CHECK-NEXT: lfd f1, 0(r27)
887887
; CHECK-NEXT: xsmuldp f0, f0, f1
888-
; CHECK-NEXT: lfdx f1, r28, r9
888+
; CHECK-NEXT: lfdx f1, r26, r9
889889
; CHECK-NEXT: xsadddp f0, f1, f0
890-
; CHECK-NEXT: stfdx f0, r28, r9
891-
; CHECK-NEXT: lfdx f0, r26, r7
890+
; CHECK-NEXT: stfdx f0, r26, r9
891+
; CHECK-NEXT: lfdx f0, r28, r7
892892
; CHECK-NEXT: lfdx f1, r27, r7
893893
; CHECK-NEXT: xsmuldp f0, f0, f1
894894
; CHECK-NEXT: lfdx f1, r29, r9
895895
; CHECK-NEXT: xsadddp f0, f1, f0
896896
; CHECK-NEXT: stfdx f0, r29, r9
897-
; CHECK-NEXT: lfdx f0, r26, r8
897+
; CHECK-NEXT: lfdx f0, r28, r8
898898
; CHECK-NEXT: lfdx f1, r27, r8
899-
; CHECK-NEXT: add r26, r26, r12
899+
; CHECK-NEXT: add r28, r28, r12
900900
; CHECK-NEXT: add r27, r27, r12
901901
; CHECK-NEXT: xsmuldp f0, f0, f1
902902
; CHECK-NEXT: lfdx f1, r30, r9
Lines changed: 71 additions & 38 deletions
Original file line numberDiff line numberDiff line change
@@ -1,34 +1,28 @@
1-
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
1+
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
22
; RUN: opt -S -passes=licm < %s | FileCheck %s
33

4-
; Adapted from
4+
; Adapted from:
55
; for(long i = 0; i < n; ++i)
6-
; a[i] = (i+1) * v;
7-
define void @test1(i64 %n) {
8-
; CHECK-LABEL: define void @test1(
9-
; CHECK-SAME: i64 [[N:%.*]]) {
6+
; a[i] = (i*k) * v;
7+
define void @test(i64 %n, i64 %k) {
8+
; CHECK-LABEL: @test(
109
; CHECK-NEXT: entry:
1110
; CHECK-NEXT: br label [[FOR_PH:%.*]]
1211
; CHECK: for.ph:
13-
; CHECK-NEXT: [[VSCALE:%.*]] = tail call i64 @llvm.vscale.i64()
14-
; CHECK-NEXT: [[VSCALE_2:%.*]] = shl nuw nsw i64 [[VSCALE]], 1
15-
; CHECK-NEXT: [[VSCALE_4:%.*]] = shl nuw nsw i64 [[VSCALE]], 2
16-
; CHECK-NEXT: [[VEC_INIT:%.*]] = insertelement <vscale x 2 x i64> zeroinitializer, i64 1, i64 1
17-
; CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 2 x i64> poison, i64 [[VSCALE_2]], i64 0
18-
; CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <vscale x 2 x i64> [[DOTSPLATINSERT]], <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
19-
; CHECK-NEXT: [[INVARIANT_OP:%.*]] = add <vscale x 2 x i64> [[DOTSPLAT]], shufflevector (<vscale x 2 x i64> insertelement (<vscale x 2 x i64> poison, i64 1, i64 0), <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer)
20-
; CHECK-NEXT: [[INVARIANT_OP1:%.*]] = add <vscale x 2 x i64> [[DOTSPLAT]], [[DOTSPLAT]]
12+
; CHECK-NEXT: [[K_2:%.*]] = shl nuw nsw i64 [[K:%.*]], 1
13+
; CHECK-NEXT: [[VEC_INIT:%.*]] = insertelement <2 x i64> zeroinitializer, i64 [[K]], i64 1
14+
; CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <2 x i64> poison, i64 [[K_2]], i64 0
15+
; CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <2 x i64> [[DOTSPLATINSERT]], <2 x i64> poison, <2 x i32> zeroinitializer
16+
; CHECK-NEXT: [[INVARIANT_OP:%.*]] = add <2 x i64> [[DOTSPLAT]], [[DOTSPLAT]]
2117
; CHECK-NEXT: br label [[FOR_BODY:%.*]]
2218
; CHECK: for.body:
2319
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[FOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[FOR_BODY]] ]
24-
; CHECK-NEXT: [[VEC_IND:%.*]] = phi <vscale x 2 x i64> [ [[VEC_INIT]], [[FOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[FOR_BODY]] ]
25-
; CHECK-NEXT: [[ADD1:%.*]] = add nuw nsw <vscale x 2 x i64> [[VEC_IND]], shufflevector (<vscale x 2 x i64> insertelement (<vscale x 2 x i64> poison, i64 1, i64 0), <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer)
26-
; CHECK-NEXT: [[ADD2:%.*]] = add <vscale x 2 x i64> [[VEC_IND]], [[INVARIANT_OP]]
27-
; CHECK-NEXT: call void @use(<vscale x 2 x i64> [[ADD1]])
28-
; CHECK-NEXT: call void @use(<vscale x 2 x i64> [[ADD2]])
29-
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[VSCALE_4]]
30-
; CHECK-NEXT: [[VEC_IND_NEXT]] = add <vscale x 2 x i64> [[VEC_IND]], [[INVARIANT_OP1]]
31-
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N]]
20+
; CHECK-NEXT: [[VEC_IND:%.*]] = phi <2 x i64> [ [[VEC_INIT]], [[FOR_PH]] ], [ [[VEC_IND_NEXT_REASS:%.*]], [[FOR_BODY]] ]
21+
; CHECK-NEXT: [[STEP_ADD:%.*]] = add <2 x i64> [[VEC_IND]], [[DOTSPLAT]]
22+
; CHECK-NEXT: call void @use(<2 x i64> [[STEP_ADD]])
23+
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
24+
; CHECK-NEXT: [[VEC_IND_NEXT_REASS]] = add <2 x i64> [[VEC_IND]], [[INVARIANT_OP]]
25+
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N:%.*]]
3226
; CHECK-NEXT: br i1 [[CMP]], label [[FOR_END:%.*]], label [[FOR_BODY]]
3327
; CHECK: for.end:
3428
; CHECK-NEXT: ret void
@@ -37,30 +31,69 @@ entry:
3731
br label %for.ph
3832

3933
for.ph:
40-
%vscale = tail call i64 @llvm.vscale.i64()
41-
%vscale.2 = shl nuw nsw i64 %vscale, 1
42-
%vscale.4 = shl nuw nsw i64 %vscale, 2
43-
%vec.init = insertelement <vscale x 2 x i64> zeroinitializer, i64 1, i64 1
44-
%.splatinsert = insertelement <vscale x 2 x i64> poison, i64 %vscale.2, i64 0
45-
%.splat = shufflevector <vscale x 2 x i64> %.splatinsert, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
34+
%k.2 = shl nuw nsw i64 %k, 1
35+
%vec.init = insertelement <2 x i64> zeroinitializer, i64 %k, i64 1
36+
%.splatinsert = insertelement <2 x i64> poison, i64 %k.2, i64 0
37+
%.splat = shufflevector <2 x i64> %.splatinsert, <2 x i64> poison, <2 x i32> zeroinitializer
4638
br label %for.body
4739

4840
for.body:
4941
%index = phi i64 [ 0, %for.ph ], [ %index.next, %for.body ]
50-
%vec.ind = phi <vscale x 2 x i64> [ %vec.init, %for.ph ], [ %vec.ind.next, %for.body ]
51-
%step.add = add <vscale x 2 x i64> %vec.ind, %.splat
52-
%add1 = add nuw nsw <vscale x 2 x i64> %vec.ind, shufflevector (<vscale x 2 x i64> insertelement (<vscale x 2 x i64> poison, i64 1, i64 0), <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer)
53-
%add2 = add nuw nsw <vscale x 2 x i64> %step.add, shufflevector (<vscale x 2 x i64> insertelement (<vscale x 2 x i64> poison, i64 1, i64 0), <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer)
54-
call void @use(<vscale x 2 x i64> %add1)
55-
call void @use(<vscale x 2 x i64> %add2)
56-
%index.next = add nuw i64 %index, %vscale.4
57-
%vec.ind.next = add <vscale x 2 x i64> %step.add, %.splat
42+
%vec.ind = phi <2 x i64> [ %vec.init, %for.ph ], [ %vec.ind.next, %for.body ]
43+
%step.add = add <2 x i64> %vec.ind, %.splat
44+
call void @use(<2 x i64> %step.add)
45+
%index.next = add nuw i64 %index, 4
46+
%vec.ind.next = add <2 x i64> %step.add, %.splat
5847
%cmp = icmp eq i64 %index.next, %n
5948
br i1 %cmp, label %for.end, label %for.body
6049

6150
for.end:
6251
ret void
6352
}
6453

65-
declare i64 @llvm.vscale.i64()
66-
declare void @use(<vscale x 2 x i64>)
54+
; Same as above but `%step.add` is unused and thus removed.
55+
define void @test_single_use(i64 %n, i64 %k) {
56+
; CHECK-LABEL: @test_single_use(
57+
; CHECK-NEXT: entry:
58+
; CHECK-NEXT: br label [[FOR_PH:%.*]]
59+
; CHECK: for.ph:
60+
; CHECK-NEXT: [[K_2:%.*]] = shl nuw nsw i64 [[K:%.*]], 1
61+
; CHECK-NEXT: [[VEC_INIT:%.*]] = insertelement <2 x i64> zeroinitializer, i64 [[K]], i64 1
62+
; CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <2 x i64> poison, i64 [[K_2]], i64 0
63+
; CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <2 x i64> [[DOTSPLATINSERT]], <2 x i64> poison, <2 x i32> zeroinitializer
64+
; CHECK-NEXT: [[INVARIANT_OP:%.*]] = add <2 x i64> [[DOTSPLAT]], [[DOTSPLAT]]
65+
; CHECK-NEXT: br label [[FOR_BODY:%.*]]
66+
; CHECK: for.body:
67+
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[FOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[FOR_BODY]] ]
68+
; CHECK-NEXT: [[VEC_IND:%.*]] = phi <2 x i64> [ [[VEC_INIT]], [[FOR_PH]] ], [ [[VEC_IND_NEXT_REASS:%.*]], [[FOR_BODY]] ]
69+
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
70+
; CHECK-NEXT: [[VEC_IND_NEXT_REASS]] = add <2 x i64> [[VEC_IND]], [[INVARIANT_OP]]
71+
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N:%.*]]
72+
; CHECK-NEXT: br i1 [[CMP]], label [[FOR_END:%.*]], label [[FOR_BODY]]
73+
; CHECK: for.end:
74+
; CHECK-NEXT: ret void
75+
;
76+
entry:
77+
br label %for.ph
78+
79+
for.ph:
80+
%k.2 = shl nuw nsw i64 %k, 1
81+
%vec.init = insertelement <2 x i64> zeroinitializer, i64 %k, i64 1
82+
%.splatinsert = insertelement <2 x i64> poison, i64 %k.2, i64 0
83+
%.splat = shufflevector <2 x i64> %.splatinsert, <2 x i64> poison, <2 x i32> zeroinitializer
84+
br label %for.body
85+
86+
for.body:
87+
%index = phi i64 [ 0, %for.ph ], [ %index.next, %for.body ]
88+
%vec.ind = phi <2 x i64> [ %vec.init, %for.ph ], [ %vec.ind.next, %for.body ]
89+
%step.add = add <2 x i64> %vec.ind, %.splat
90+
%index.next = add nuw i64 %index, 4
91+
%vec.ind.next = add <2 x i64> %step.add, %.splat
92+
%cmp = icmp eq i64 %index.next, %n
93+
br i1 %cmp, label %for.end, label %for.body
94+
95+
for.end:
96+
ret void
97+
}
98+
99+
declare void @use(<2 x i64>)

llvm/test/Transforms/LICM/sink-foldable.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -79,7 +79,7 @@ define ptr @test2(i32 %j, ptr readonly %P, ptr readnone %Q) {
7979
; CHECK-NEXT: entry:
8080
; CHECK-NEXT: br label [[FOR_BODY:%.*]]
8181
; CHECK: for.cond:
82-
; CHECK-NEXT: [[I_ADDR_0:%.*]] = phi i32 [ [[ADD:%.*]], [[IF_END:%.*]] ]
82+
; CHECK-NEXT: [[I_ADDR_0:%.*]] = phi i32 [ [[ADD_REASS:%.*]], [[IF_END:%.*]] ]
8383
; CHECK-NEXT: [[P_ADDR_0:%.*]] = phi ptr [ [[ADD_PTR:%.*]], [[IF_END]] ]
8484
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[I_ADDR_0]], [[J:%.*]]
8585
; CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY]], label [[LOOPEXIT0:%.*]]
@@ -97,7 +97,7 @@ define ptr @test2(i32 %j, ptr readonly %P, ptr readnone %Q) {
9797
; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds ptr, ptr [[ADD_PTR]], i64 [[IDX2_EXT]]
9898
; CHECK-NEXT: [[L1:%.*]] = load ptr, ptr [[ARRAYIDX2]], align 8
9999
; CHECK-NEXT: [[CMP2:%.*]] = icmp ugt ptr [[L1]], [[Q]]
100-
; CHECK-NEXT: [[ADD]] = add i32 [[I_ADDR]], 2
100+
; CHECK-NEXT: [[ADD_REASS]] = add nsw i32 [[I_ADDR]], 2
101101
; CHECK-NEXT: br i1 [[CMP2]], label [[LOOPEXIT2:%.*]], label [[FOR_COND]]
102102
; CHECK: loopexit0:
103103
; CHECK-NEXT: [[P0:%.*]] = phi ptr [ null, [[FOR_COND]] ]

llvm/test/Transforms/LICM/update-scev-after-hoist.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22

33
define i16 @main() {
44
; SCEV-EXPR: Classifying expressions for: @main
5-
; SCEV-EXPR-NEXT: %mul = phi i16 [ 1, %entry ], [ %mul.n.3, %loop ]
5+
; SCEV-EXPR-NEXT: %mul = phi i16 [ 1, %entry ], [ %mul.n.3.reass, %loop ]
66
; SCEV-EXPR-NEXT: --> %mul U: [0,-15) S: [-32768,32753) Exits: 4096 LoopDispositions: { %loop: Variant }
77
; SCEV-EXPR-NEXT: %div = phi i16 [ 32767, %entry ], [ %div.n.3, %loop ]
88
; SCEV-EXPR-NEXT: --> %div U: [-2048,-32768) S: [-2048,-32768) Exits: 7 LoopDispositions: { %loop: Variant }

0 commit comments

Comments
 (0)