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optimisanoptimisan
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format and sort registry
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+90
-93
lines changed

2 files changed

+90
-93
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -103,8 +103,8 @@ MACHINE_FUNCTION_PASS("amdgpu-reserve-wwm-regs", AMDGPUReserveWWMRegsPass())
103103
MACHINE_FUNCTION_PASS("amdgpu-rewrite-partial-reg-uses", GCNRewritePartialRegUsesPass())
104104
MACHINE_FUNCTION_PASS("amdgpu-pre-ra-optimizations", GCNPreRAOptimizationsPass())
105105
MACHINE_FUNCTION_PASS("amdgpu-nsa-reassign", GCNNSAReassignPass())
106-
MACHINE_FUNCTION_PASS("gcn-dpp-combine", GCNDPPCombinePass())
107106
MACHINE_FUNCTION_PASS("gcn-create-vopd", GCNCreateVOPDPass())
107+
MACHINE_FUNCTION_PASS("gcn-dpp-combine", GCNDPPCombinePass())
108108
MACHINE_FUNCTION_PASS("si-fix-sgpr-copies", SIFixSGPRCopiesPass())
109109
MACHINE_FUNCTION_PASS("si-fix-vgpr-copies", SIFixVGPRCopiesPass())
110110
MACHINE_FUNCTION_PASS("si-fold-operands", SIFoldOperandsPass());

‎llvm/lib/Target/AMDGPU/GCNCreateVOPD.cpp

Lines changed: 89 additions & 92 deletions
Original file line numberDiff line numberDiff line change
@@ -49,108 +49,105 @@ class GCNCreateVOPD {
4949
MachineInstr *SecondMI;
5050
};
5151

52-
public:
53-
const GCNSubtarget *ST = nullptr;
54-
55-
bool doReplace(const SIInstrInfo *SII, VOPDCombineInfo &CI) {
56-
auto *FirstMI = CI.FirstMI;
57-
auto *SecondMI = CI.SecondMI;
58-
unsigned Opc1 = FirstMI->getOpcode();
59-
unsigned Opc2 = SecondMI->getOpcode();
60-
unsigned EncodingFamily =
61-
AMDGPU::getVOPDEncodingFamily(SII->getSubtarget());
62-
int NewOpcode =
63-
AMDGPU::getVOPDFull(AMDGPU::getVOPDOpcode(Opc1),
64-
AMDGPU::getVOPDOpcode(Opc2), EncodingFamily);
65-
assert(NewOpcode != -1 &&
66-
"Should have previously determined this as a possible VOPD\n");
67-
68-
auto VOPDInst =
69-
BuildMI(*FirstMI->getParent(), FirstMI, FirstMI->getDebugLoc(),
70-
SII->get(NewOpcode))
71-
.setMIFlags(FirstMI->getFlags() | SecondMI->getFlags());
72-
73-
namespace VOPD = AMDGPU::VOPD;
74-
MachineInstr *MI[] = {FirstMI, SecondMI};
75-
auto InstInfo =
76-
AMDGPU::getVOPDInstInfo(FirstMI->getDesc(), SecondMI->getDesc());
77-
78-
for (auto CompIdx : VOPD::COMPONENTS) {
79-
auto MCOprIdx = InstInfo[CompIdx].getIndexOfDstInMCOperands();
80-
VOPDInst.add(MI[CompIdx]->getOperand(MCOprIdx));
81-
}
52+
public:
53+
const GCNSubtarget *ST = nullptr;
54+
55+
bool doReplace(const SIInstrInfo *SII, VOPDCombineInfo &CI) {
56+
auto *FirstMI = CI.FirstMI;
57+
auto *SecondMI = CI.SecondMI;
58+
unsigned Opc1 = FirstMI->getOpcode();
59+
unsigned Opc2 = SecondMI->getOpcode();
60+
unsigned EncodingFamily =
61+
AMDGPU::getVOPDEncodingFamily(SII->getSubtarget());
62+
int NewOpcode =
63+
AMDGPU::getVOPDFull(AMDGPU::getVOPDOpcode(Opc1),
64+
AMDGPU::getVOPDOpcode(Opc2), EncodingFamily);
65+
assert(NewOpcode != -1 &&
66+
"Should have previously determined this as a possible VOPD\n");
67+
68+
auto VOPDInst = BuildMI(*FirstMI->getParent(), FirstMI,
69+
FirstMI->getDebugLoc(), SII->get(NewOpcode))
70+
.setMIFlags(FirstMI->getFlags() | SecondMI->getFlags());
71+
72+
namespace VOPD = AMDGPU::VOPD;
73+
MachineInstr *MI[] = {FirstMI, SecondMI};
74+
auto InstInfo =
75+
AMDGPU::getVOPDInstInfo(FirstMI->getDesc(), SecondMI->getDesc());
76+
77+
for (auto CompIdx : VOPD::COMPONENTS) {
78+
auto MCOprIdx = InstInfo[CompIdx].getIndexOfDstInMCOperands();
79+
VOPDInst.add(MI[CompIdx]->getOperand(MCOprIdx));
80+
}
8281

83-
for (auto CompIdx : VOPD::COMPONENTS) {
84-
auto CompSrcOprNum = InstInfo[CompIdx].getCompSrcOperandsNum();
85-
for (unsigned CompSrcIdx = 0; CompSrcIdx < CompSrcOprNum;
86-
++CompSrcIdx) {
87-
auto MCOprIdx =
88-
InstInfo[CompIdx].getIndexOfSrcInMCOperands(CompSrcIdx);
89-
VOPDInst.add(MI[CompIdx]->getOperand(MCOprIdx));
90-
}
82+
for (auto CompIdx : VOPD::COMPONENTS) {
83+
auto CompSrcOprNum = InstInfo[CompIdx].getCompSrcOperandsNum();
84+
for (unsigned CompSrcIdx = 0; CompSrcIdx < CompSrcOprNum; ++CompSrcIdx) {
85+
auto MCOprIdx = InstInfo[CompIdx].getIndexOfSrcInMCOperands(CompSrcIdx);
86+
VOPDInst.add(MI[CompIdx]->getOperand(MCOprIdx));
9187
}
88+
}
9289

93-
SII->fixImplicitOperands(*VOPDInst);
94-
for (auto CompIdx : VOPD::COMPONENTS)
95-
VOPDInst.copyImplicitOps(*MI[CompIdx]);
90+
SII->fixImplicitOperands(*VOPDInst);
91+
for (auto CompIdx : VOPD::COMPONENTS)
92+
VOPDInst.copyImplicitOps(*MI[CompIdx]);
9693

97-
LLVM_DEBUG(dbgs() << "VOPD Fused: " << *VOPDInst << " from\tX: "
98-
<< *CI.FirstMI << "\tY: " << *CI.SecondMI << "\n");
94+
LLVM_DEBUG(dbgs() << "VOPD Fused: " << *VOPDInst << " from\tX: "
95+
<< *CI.FirstMI << "\tY: " << *CI.SecondMI << "\n");
9996

100-
for (auto CompIdx : VOPD::COMPONENTS)
101-
MI[CompIdx]->eraseFromParent();
97+
for (auto CompIdx : VOPD::COMPONENTS)
98+
MI[CompIdx]->eraseFromParent();
10299

103-
++NumVOPDCreated;
104-
return true;
105-
}
100+
++NumVOPDCreated;
101+
return true;
102+
}
106103

107-
bool run(MachineFunction &MF) {
108-
ST = &MF.getSubtarget<GCNSubtarget>();
109-
if (!AMDGPU::hasVOPD(*ST) || !ST->isWave32())
110-
return false;
111-
LLVM_DEBUG(dbgs() << "CreateVOPD Pass:\n");
112-
113-
const SIInstrInfo *SII = ST->getInstrInfo();
114-
bool Changed = false;
115-
116-
SmallVector<VOPDCombineInfo> ReplaceCandidates;
117-
118-
for (auto &MBB : MF) {
119-
auto MII = MBB.begin(), E = MBB.end();
120-
while (MII != E) {
121-
auto *FirstMI = &*MII;
122-
MII = next_nodbg(MII, MBB.end());
123-
if (MII == MBB.end())
124-
break;
125-
if (FirstMI->isDebugInstr())
126-
continue;
127-
auto *SecondMI = &*MII;
128-
unsigned Opc = FirstMI->getOpcode();
129-
unsigned Opc2 = SecondMI->getOpcode();
130-
llvm::AMDGPU::CanBeVOPD FirstCanBeVOPD = AMDGPU::getCanBeVOPD(Opc);
131-
llvm::AMDGPU::CanBeVOPD SecondCanBeVOPD = AMDGPU::getCanBeVOPD(Opc2);
132-
VOPDCombineInfo CI;
133-
134-
if (FirstCanBeVOPD.X && SecondCanBeVOPD.Y)
135-
CI = VOPDCombineInfo(FirstMI, SecondMI);
136-
else if (FirstCanBeVOPD.Y && SecondCanBeVOPD.X)
137-
CI = VOPDCombineInfo(SecondMI, FirstMI);
138-
else
139-
continue;
140-
// checkVOPDRegConstraints cares about program order, but doReplace
141-
// cares about X-Y order in the constituted VOPD
142-
if (llvm::checkVOPDRegConstraints(*SII, *FirstMI, *SecondMI)) {
143-
ReplaceCandidates.push_back(CI);
144-
++MII;
145-
}
104+
bool run(MachineFunction &MF) {
105+
ST = &MF.getSubtarget<GCNSubtarget>();
106+
if (!AMDGPU::hasVOPD(*ST) || !ST->isWave32())
107+
return false;
108+
LLVM_DEBUG(dbgs() << "CreateVOPD Pass:\n");
109+
110+
const SIInstrInfo *SII = ST->getInstrInfo();
111+
bool Changed = false;
112+
113+
SmallVector<VOPDCombineInfo> ReplaceCandidates;
114+
115+
for (auto &MBB : MF) {
116+
auto MII = MBB.begin(), E = MBB.end();
117+
while (MII != E) {
118+
auto *FirstMI = &*MII;
119+
MII = next_nodbg(MII, MBB.end());
120+
if (MII == MBB.end())
121+
break;
122+
if (FirstMI->isDebugInstr())
123+
continue;
124+
auto *SecondMI = &*MII;
125+
unsigned Opc = FirstMI->getOpcode();
126+
unsigned Opc2 = SecondMI->getOpcode();
127+
llvm::AMDGPU::CanBeVOPD FirstCanBeVOPD = AMDGPU::getCanBeVOPD(Opc);
128+
llvm::AMDGPU::CanBeVOPD SecondCanBeVOPD = AMDGPU::getCanBeVOPD(Opc2);
129+
VOPDCombineInfo CI;
130+
131+
if (FirstCanBeVOPD.X && SecondCanBeVOPD.Y)
132+
CI = VOPDCombineInfo(FirstMI, SecondMI);
133+
else if (FirstCanBeVOPD.Y && SecondCanBeVOPD.X)
134+
CI = VOPDCombineInfo(SecondMI, FirstMI);
135+
else
136+
continue;
137+
// checkVOPDRegConstraints cares about program order, but doReplace
138+
// cares about X-Y order in the constituted VOPD
139+
if (llvm::checkVOPDRegConstraints(*SII, *FirstMI, *SecondMI)) {
140+
ReplaceCandidates.push_back(CI);
141+
++MII;
146142
}
147143
}
148-
for (auto &CI : ReplaceCandidates) {
149-
Changed |= doReplace(SII, CI);
150-
}
151-
152-
return Changed;
153144
}
145+
for (auto &CI : ReplaceCandidates) {
146+
Changed |= doReplace(SII, CI);
147+
}
148+
149+
return Changed;
150+
}
154151
};
155152

156153
class GCNCreateVOPDLegacy : public MachineFunctionPass {

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