Skip to content

Commit 1f51e37

Browse files
committed
[RISCV] XLenVT -> i64
1 parent 7e3540d commit 1f51e37

File tree

1 file changed

+2
-2
lines changed

1 file changed

+2
-2
lines changed

llvm/lib/Target/RISCV/RISCVInstrInfo.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2120,7 +2120,7 @@ def : Pat<(XLenVT (add GPR:$rs1, immop_oneuse<AddiPair>:$rs2)),
21202120
(ADDI (XLenVT (ADDI GPR:$rs1, (AddiPairImmLarge imm:$rs2))),
21212121
(AddiPairImmSmall imm:$rs2))>;
21222122

2123-
def negImm : ComplexPattern<XLenVT, 1, "selectNegImm", [], [], 0>;
2123+
def negImm : ComplexPattern<i64, 1, "selectNegImm", [], [], 0>;
21242124

21252125
let Predicates = [IsRV64] in {
21262126
// Select W instructions if only the lower 32-bits of the result are used.
@@ -2129,7 +2129,7 @@ def : Pat<(binop_allwusers<add> GPR:$rs1, immop_oneuse<AddiPair>:$rs2),
21292129
(AddiPairImmSmall imm:$rs2))>;
21302130

21312131
// Select SUB if the negated constant is cheaper to materialize.
2132-
def : Pat<(XLenVT (add GPR:$rs1, negImm:$rs2)), (SUB GPR:$rs1, negImm:$rs2)>;
2132+
def : Pat<(i64 (add GPR:$rs1, negImm:$rs2)), (SUB GPR:$rs1, negImm:$rs2)>;
21332133
}
21342134

21352135
//===----------------------------------------------------------------------===//

0 commit comments

Comments
 (0)