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Revert "[AArch64][SVE] Improve fixed-length addressing modes." (#130263)
This reverts commit f01e760.
1 parent 52bc812 commit 21610e3

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5 files changed

+54
-434
lines changed

5 files changed

+54
-434
lines changed

clang/test/CodeGen/AArch64/sve-vector-bits-codegen.c

+6-3
Original file line numberDiff line numberDiff line change
@@ -13,9 +13,12 @@
1313

1414
void func(int *restrict a, int *restrict b) {
1515
// CHECK-LABEL: func
16-
// CHECK256-COUNT-8: str
17-
// CHECK512-COUNT-4: str
18-
// CHECK1024-COUNT-2: str
16+
// CHECK256-COUNT-1: str
17+
// CHECK256-COUNT-7: st1w
18+
// CHECK512-COUNT-1: str
19+
// CHECK512-COUNT-3: st1w
20+
// CHECK1024-COUNT-1: str
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// CHECK1024-COUNT-1: st1w
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// CHECK2048-COUNT-1: st1w
2023
#pragma clang loop vectorize(enable)
2124
for (int i = 0; i < 64; ++i)

llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp

+2-13
Original file line numberDiff line numberDiff line change
@@ -7380,23 +7380,12 @@ bool AArch64DAGToDAGISel::SelectAddrModeIndexedSVE(SDNode *Root, SDValue N,
73807380
return false;
73817381

73827382
SDValue VScale = N.getOperand(1);
7383-
int64_t MulImm = std::numeric_limits<int64_t>::max();
7384-
if (VScale.getOpcode() == ISD::VSCALE) {
7385-
MulImm = cast<ConstantSDNode>(VScale.getOperand(0))->getSExtValue();
7386-
} else if (auto C = dyn_cast<ConstantSDNode>(VScale)) {
7387-
int64_t ByteOffset = C->getSExtValue();
7388-
const auto KnownVScale =
7389-
Subtarget->getSVEVectorSizeInBits() / AArch64::SVEBitsPerBlock;
7390-
7391-
if (!KnownVScale || ByteOffset % KnownVScale != 0)
7392-
return false;
7393-
7394-
MulImm = ByteOffset / KnownVScale;
7395-
} else
7383+
if (VScale.getOpcode() != ISD::VSCALE)
73967384
return false;
73977385

73987386
TypeSize TS = MemVT.getSizeInBits();
73997387
int64_t MemWidthBytes = static_cast<int64_t>(TS.getKnownMinValue()) / 8;
7388+
int64_t MulImm = cast<ConstantSDNode>(VScale.getOperand(0))->getSExtValue();
74007389

74017390
if ((MulImm % MemWidthBytes) != 0)
74027391
return false;

llvm/lib/Target/AArch64/AArch64Subtarget.h

+1-11
Original file line numberDiff line numberDiff line change
@@ -391,7 +391,7 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo {
391391
void mirFileLoaded(MachineFunction &MF) const override;
392392

393393
// Return the known range for the bit length of SVE data registers. A value
394-
// of 0 means nothing is known about that particular limit beyond what's
394+
// of 0 means nothing is known about that particular limit beyong what's
395395
// implied by the architecture.
396396
unsigned getMaxSVEVectorSizeInBits() const {
397397
assert(isSVEorStreamingSVEAvailable() &&
@@ -405,16 +405,6 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo {
405405
return MinSVEVectorSizeInBits;
406406
}
407407

408-
// Return the known bit length of SVE data registers. A value of 0 means the
409-
// length is unkown beyond what's implied by the architecture.
410-
unsigned getSVEVectorSizeInBits() const {
411-
assert(isSVEorStreamingSVEAvailable() &&
412-
"Tried to get SVE vector length without SVE support!");
413-
if (MinSVEVectorSizeInBits == MaxSVEVectorSizeInBits)
414-
return MaxSVEVectorSizeInBits;
415-
return 0;
416-
}
417-
418408
bool useSVEForFixedLengthVectors() const {
419409
if (!isSVEorStreamingSVEAvailable())
420410
return false;

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