[Hexagon] Avoid crash on CONCAT_VECTORS with illegal element types

Legal vector element types may not be legal as scalar types. When
CONCAT_VECTORS is converted to BUILD_VECTOR, the individual vector
elements become standalone operands to the build operation. If they
have illegal (scalar) types, they need to be made legal. In doing
so, the case of TRUNCATE was not handled, causing an assertion to
fail.

Author: Krzysztof Parzyszek

llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp

@@ -1248,12 +1248,19 @@ HexagonTargetLowering::LowerHvxConcatVectors(SDValue Op, SelectionDAG &DAG)
           continue;
         }
         // A few less complicated cases.
-        if (V.getOpcode() == ISD::Constant)
-          Elems[i] = DAG.getSExtOrTrunc(V, dl, NTy);
-        else if (V.isUndef())
-          Elems[i] = DAG.getUNDEF(NTy);
-        else
-          llvm_unreachable("Unexpected vector element");
+        switch (V.getOpcode()) {
+          case ISD::Constant:
+            Elems[i] = DAG.getSExtOrTrunc(V, dl, NTy);
+            break;
+          case ISD::UNDEF:
+            Elems[i] = DAG.getUNDEF(NTy);
+            break;
+          case ISD::TRUNCATE:
+            Elems[i] = V.getOperand(0);
+            break;
+          default:
+            llvm_unreachable("Unexpected vector element");
+        }
       }
     }
     return DAG.getBuildVector(VecTy, dl, Elems);

llvm/test/CodeGen/Hexagon/autohvx/isel-hvx-concat-truncate.ll

@@ -0,0 +1,26 @@
+; RUN: llc -march=hexagon -hexagon-hvx-widen=32 < %s | FileCheck %s
+
+; Check that this doesn't crash.
+; CHECK: memw
+
+target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
+target triple = "hexagon"
+
+define dllexport void @f0(i8* %a0) #0 {
+b0:
+  %v0 = bitcast i8* %a0 to i32*
+  %v1 = getelementptr inbounds i32, i32* %v0, i32 undef
+  %v2 = bitcast i32* %v1 to <7 x i32>*
+  %v3 = load i8, i8* undef, align 1
+  %v4 = insertelement <7 x i8> undef, i8 %v3, i32 0
+  %v5 = shufflevector <7 x i8> %v4, <7 x i8> undef, <7 x i32> zeroinitializer
+  %v6 = zext <7 x i8> %v5 to <7 x i32>
+  %v7 = load <7 x i8>, <7 x i8>* undef, align 1
+  %v8 = zext <7 x i8> %v7 to <7 x i32>
+  %v9 = mul nsw <7 x i32> %v6, %v8
+  %v10 = add nsw <7 x i32> %v9, zeroinitializer
+  store <7 x i32> %v10, <7 x i32>* %v2, align 4
+  ret void
+}
+
+attributes #0 = { "target-features"="+hvx,+hvx-length128b" }