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[RISCV] Remove unecessary early exit in transferBefore (#74040)
Previously we bailed if we encountered a pseudo without a VL op, i.e. vmv.x.s, which prevented us from preserving VL and VTYPE. It looks like this was copied over from a time whenever this code was operating on the MachineInstrs in place, see https://reviews.llvm.org/D127870 However because we no longer mutate the MIs, we can just get rid of this early exit which allows us to preserve VL and VTYPE when dealing with vmv.x.s.
1 parent c4ac1d2 commit 3944504

14 files changed

+313
-455
lines changed

‎llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

-5
Original file line numberDiff line numberDiff line change
@@ -1062,11 +1062,6 @@ void RISCVInsertVSETVLI::transferBefore(VSETVLIInfo &Info,
10621062
if (Info.hasSEWLMULRatioOnly() || !Info.isValid() || Info.isUnknown())
10631063
Info = NewInfo;
10641064

1065-
if (!RISCVII::hasVLOp(TSFlags)) {
1066-
Info = NewInfo;
1067-
return;
1068-
}
1069-
10701065
DemandedFields Demanded = getDemanded(MI, MRI, ST);
10711066
const VSETVLIInfo IncomingInfo =
10721067
adjustIncoming(PrevInfo, NewInfo, Demanded, MRI);

‎llvm/test/CodeGen/RISCV/65704-illegal-instruction.ll

+3-3
Original file line numberDiff line numberDiff line change
@@ -22,11 +22,11 @@ define void @foo(<vscale x 8 x i8> %0) {
2222
; CHECK-NEXT: vmv.v.i v9, 0
2323
; CHECK-NEXT: vsetivli zero, 0, e8, m1, tu, ma
2424
; CHECK-NEXT: vslideup.vi v9, v10, 0
25-
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
25+
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
2626
; CHECK-NEXT: vmv.x.s s0, v9
27-
; CHECK-NEXT: vsetivli zero, 0, e8, m1, tu, ma
27+
; CHECK-NEXT: vsetvli zero, zero, e8, m1, tu, ma
2828
; CHECK-NEXT: vslideup.vi v8, v9, 0
29-
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
29+
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
3030
; CHECK-NEXT: vmv.x.s s1, v8
3131
; CHECK-NEXT: .LBB0_1: # =>This Inner Loop Header: Depth=1
3232
; CHECK-NEXT: li a1, 0

‎llvm/test/CodeGen/RISCV/double_reduct.ll

+1-1
Original file line numberDiff line numberDiff line change
@@ -113,7 +113,7 @@ define i16 @add_ext_v32i16(<32 x i8> %a, <16 x i8> %b) {
113113
; CHECK-NEXT: li a0, 32
114114
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
115115
; CHECK-NEXT: vwredsumu.vs v8, v8, v10
116-
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
116+
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
117117
; CHECK-NEXT: vmv.x.s a0, v8
118118
; CHECK-NEXT: ret
119119
%ae = zext <32 x i8> %a to <32 x i16>

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll

+10-10
Original file line numberDiff line numberDiff line change
@@ -106,7 +106,7 @@ define i1 @extractelt_v16i1(ptr %x, i64 %idx) nounwind {
106106
; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
107107
; RV32-NEXT: vle8.v v8, (a0)
108108
; RV32-NEXT: vmseq.vi v8, v8, 0
109-
; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
109+
; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, ma
110110
; RV32-NEXT: vmv.x.s a0, v8
111111
; RV32-NEXT: srl a0, a0, a1
112112
; RV32-NEXT: andi a0, a0, 1
@@ -117,7 +117,7 @@ define i1 @extractelt_v16i1(ptr %x, i64 %idx) nounwind {
117117
; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma
118118
; RV64-NEXT: vle8.v v8, (a0)
119119
; RV64-NEXT: vmseq.vi v8, v8, 0
120-
; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
120+
; RV64-NEXT: vsetvli zero, zero, e16, m2, ta, ma
121121
; RV64-NEXT: vmv.x.s a0, v8
122122
; RV64-NEXT: srl a0, a0, a1
123123
; RV64-NEXT: andi a0, a0, 1
@@ -128,7 +128,7 @@ define i1 @extractelt_v16i1(ptr %x, i64 %idx) nounwind {
128128
; RV32ZBS-NEXT: vsetivli zero, 16, e8, m1, ta, ma
129129
; RV32ZBS-NEXT: vle8.v v8, (a0)
130130
; RV32ZBS-NEXT: vmseq.vi v8, v8, 0
131-
; RV32ZBS-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
131+
; RV32ZBS-NEXT: vsetvli zero, zero, e16, m2, ta, ma
132132
; RV32ZBS-NEXT: vmv.x.s a0, v8
133133
; RV32ZBS-NEXT: bext a0, a0, a1
134134
; RV32ZBS-NEXT: ret
@@ -138,7 +138,7 @@ define i1 @extractelt_v16i1(ptr %x, i64 %idx) nounwind {
138138
; RV64ZBS-NEXT: vsetivli zero, 16, e8, m1, ta, ma
139139
; RV64ZBS-NEXT: vle8.v v8, (a0)
140140
; RV64ZBS-NEXT: vmseq.vi v8, v8, 0
141-
; RV64ZBS-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
141+
; RV64ZBS-NEXT: vsetvli zero, zero, e16, m2, ta, ma
142142
; RV64ZBS-NEXT: vmv.x.s a0, v8
143143
; RV64ZBS-NEXT: bext a0, a0, a1
144144
; RV64ZBS-NEXT: ret
@@ -155,7 +155,7 @@ define i1 @extractelt_v32i1(ptr %x, i64 %idx) nounwind {
155155
; RV32-NEXT: vsetvli zero, a2, e8, m2, ta, ma
156156
; RV32-NEXT: vle8.v v8, (a0)
157157
; RV32-NEXT: vmseq.vi v10, v8, 0
158-
; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
158+
; RV32-NEXT: vsetvli zero, zero, e32, m8, ta, ma
159159
; RV32-NEXT: vmv.x.s a0, v10
160160
; RV32-NEXT: srl a0, a0, a1
161161
; RV32-NEXT: andi a0, a0, 1
@@ -167,7 +167,7 @@ define i1 @extractelt_v32i1(ptr %x, i64 %idx) nounwind {
167167
; RV64-NEXT: vsetvli zero, a2, e8, m2, ta, ma
168168
; RV64-NEXT: vle8.v v8, (a0)
169169
; RV64-NEXT: vmseq.vi v10, v8, 0
170-
; RV64-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
170+
; RV64-NEXT: vsetvli zero, zero, e32, m8, ta, ma
171171
; RV64-NEXT: vmv.x.s a0, v10
172172
; RV64-NEXT: srl a0, a0, a1
173173
; RV64-NEXT: andi a0, a0, 1
@@ -179,7 +179,7 @@ define i1 @extractelt_v32i1(ptr %x, i64 %idx) nounwind {
179179
; RV32ZBS-NEXT: vsetvli zero, a2, e8, m2, ta, ma
180180
; RV32ZBS-NEXT: vle8.v v8, (a0)
181181
; RV32ZBS-NEXT: vmseq.vi v10, v8, 0
182-
; RV32ZBS-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
182+
; RV32ZBS-NEXT: vsetvli zero, zero, e32, m8, ta, ma
183183
; RV32ZBS-NEXT: vmv.x.s a0, v10
184184
; RV32ZBS-NEXT: bext a0, a0, a1
185185
; RV32ZBS-NEXT: ret
@@ -190,7 +190,7 @@ define i1 @extractelt_v32i1(ptr %x, i64 %idx) nounwind {
190190
; RV64ZBS-NEXT: vsetvli zero, a2, e8, m2, ta, ma
191191
; RV64ZBS-NEXT: vle8.v v8, (a0)
192192
; RV64ZBS-NEXT: vmseq.vi v10, v8, 0
193-
; RV64ZBS-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
193+
; RV64ZBS-NEXT: vsetvli zero, zero, e32, m8, ta, ma
194194
; RV64ZBS-NEXT: vmv.x.s a0, v10
195195
; RV64ZBS-NEXT: bext a0, a0, a1
196196
; RV64ZBS-NEXT: ret
@@ -221,7 +221,7 @@ define i1 @extractelt_v64i1(ptr %x, i64 %idx) nounwind {
221221
; RV64-NEXT: vsetvli zero, a2, e8, m4, ta, ma
222222
; RV64-NEXT: vle8.v v8, (a0)
223223
; RV64-NEXT: vmseq.vi v12, v8, 0
224-
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
224+
; RV64-NEXT: vsetvli zero, a2, e64, m1, ta, ma
225225
; RV64-NEXT: vmv.x.s a0, v12
226226
; RV64-NEXT: srl a0, a0, a1
227227
; RV64-NEXT: andi a0, a0, 1
@@ -246,7 +246,7 @@ define i1 @extractelt_v64i1(ptr %x, i64 %idx) nounwind {
246246
; RV64ZBS-NEXT: vsetvli zero, a2, e8, m4, ta, ma
247247
; RV64ZBS-NEXT: vle8.v v8, (a0)
248248
; RV64ZBS-NEXT: vmseq.vi v12, v8, 0
249-
; RV64ZBS-NEXT: vsetivli zero, 1, e64, m1, ta, ma
249+
; RV64ZBS-NEXT: vsetvli zero, a2, e64, m1, ta, ma
250250
; RV64ZBS-NEXT: vmv.x.s a0, v12
251251
; RV64ZBS-NEXT: bext a0, a0, a1
252252
; RV64ZBS-NEXT: ret

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