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[AMDGPU][NPM] Port SIInsertHardClauses to NPM
1 parent 6faf912 commit 39768ea

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6 files changed

+46
-18
lines changed

6 files changed

+46
-18
lines changed

llvm/lib/Target/AMDGPU/AMDGPU.h

Lines changed: 7 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -377,6 +377,12 @@ class SIInsertWaitcntsPass : public PassInfoMixin<SIInsertWaitcntsPass> {
377377
static bool isRequired() { return true; }
378378
};
379379

380+
class SIInsertHardClausesPass : public PassInfoMixin<SIInsertHardClausesPass> {
381+
public:
382+
PreservedAnalyses run(MachineFunction &MF,
383+
MachineFunctionAnalysisManager &MFAM);
384+
};
385+
380386
FunctionPass *createAMDGPUAnnotateUniformValuesLegacy();
381387

382388
ModulePass *createAMDGPUPrintfRuntimeBinding();
@@ -450,7 +456,7 @@ extern char &SIModeRegisterID;
450456
void initializeAMDGPUInsertDelayAluLegacyPass(PassRegistry &);
451457
extern char &AMDGPUInsertDelayAluID;
452458

453-
void initializeSIInsertHardClausesPass(PassRegistry &);
459+
void initializeSIInsertHardClausesLegacyPass(PassRegistry &);
454460
extern char &SIInsertHardClausesID;
455461

456462
void initializeSIInsertWaitcntsLegacyPass(PassRegistry &);

llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -109,6 +109,7 @@ MACHINE_FUNCTION_PASS("si-fix-vgpr-copies", SIFixVGPRCopiesPass())
109109
MACHINE_FUNCTION_PASS("si-fold-operands", SIFoldOperandsPass());
110110
MACHINE_FUNCTION_PASS("si-form-memory-clauses", SIFormMemoryClausesPass())
111111
MACHINE_FUNCTION_PASS("si-i1-copies", SILowerI1CopiesPass())
112+
MACHINE_FUNCTION_PASS("si-insert-hard-clauses", SIInsertHardClausesPass())
112113
MACHINE_FUNCTION_PASS("si-insert-waitcnts", SIInsertWaitcntsPass())
113114
MACHINE_FUNCTION_PASS("si-load-store-opt", SILoadStoreOptimizerPass())
114115
MACHINE_FUNCTION_PASS("si-lower-control-flow", SILowerControlFlowPass())
@@ -131,7 +132,6 @@ DUMMY_MACHINE_FUNCTION_PASS("amdgpu-pre-ra-optimizations", GCNPreRAOptimizations
131132
DUMMY_MACHINE_FUNCTION_PASS("amdgpu-rewrite-partial-reg-uses", GCNRewritePartialRegUsesPass())
132133
DUMMY_MACHINE_FUNCTION_PASS("amdgpu-set-wave-priority", AMDGPUSetWavePriorityPass())
133134

134-
DUMMY_MACHINE_FUNCTION_PASS("si-insert-hard-clauses", SIInsertHardClausesPass())
135135
DUMMY_MACHINE_FUNCTION_PASS("si-late-branch-lowering", SILateBranchLoweringPass())
136136
DUMMY_MACHINE_FUNCTION_PASS("si-pre-emit-peephole", SIPreEmitPeepholePass())
137137
// TODO: Move amdgpu-preload-kern-arg-prolog to MACHINE_FUNCTION_PASS since it

llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -534,7 +534,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
534534
initializeAMDGPUUnifyMetadataPass(*PR);
535535
initializeSIAnnotateControlFlowLegacyPass(*PR);
536536
initializeAMDGPUInsertDelayAluLegacyPass(*PR);
537-
initializeSIInsertHardClausesPass(*PR);
537+
initializeSIInsertHardClausesLegacyPass(*PR);
538538
initializeSIInsertWaitcntsLegacyPass(*PR);
539539
initializeSIModeRegisterLegacyPass(*PR);
540540
initializeSIWholeQuadModeLegacyPass(*PR);

llvm/lib/Target/AMDGPU/SIInsertHardClauses.cpp

Lines changed: 35 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -36,6 +36,7 @@
3636
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
3737
#include "llvm/ADT/SmallVector.h"
3838
#include "llvm/CodeGen/MachineFunctionPass.h"
39+
#include "llvm/CodeGen/MachinePassManager.h"
3940

4041
using namespace llvm;
4142

@@ -89,18 +90,10 @@ enum HardClauseType {
8990
HARDCLAUSE_ILLEGAL,
9091
};
9192

92-
class SIInsertHardClauses : public MachineFunctionPass {
93+
class SIInsertHardClauses {
9394
public:
94-
static char ID;
9595
const GCNSubtarget *ST = nullptr;
9696

97-
SIInsertHardClauses() : MachineFunctionPass(ID) {}
98-
99-
void getAnalysisUsage(AnalysisUsage &AU) const override {
100-
AU.setPreservesCFG();
101-
MachineFunctionPass::getAnalysisUsage(AU);
102-
}
103-
10497
HardClauseType getHardClauseType(const MachineInstr &MI) {
10598
if (MI.mayLoad() || (MI.mayStore() && ST->shouldClusterStores())) {
10699
if (ST->getGeneration() == AMDGPUSubtarget::GFX10) {
@@ -189,9 +182,7 @@ class SIInsertHardClauses : public MachineFunctionPass {
189182
return true;
190183
}
191184

192-
bool runOnMachineFunction(MachineFunction &MF) override {
193-
if (skipFunction(MF.getFunction()))
194-
return false;
185+
bool run(MachineFunction &MF) {
195186

196187
ST = &MF.getSubtarget<GCNSubtarget>();
197188
if (!ST->hasHardClauses())
@@ -265,11 +256,40 @@ class SIInsertHardClauses : public MachineFunctionPass {
265256
}
266257
};
267258

259+
class SIInsertHardClausesLegacy : public MachineFunctionPass {
260+
public:
261+
static char ID;
262+
SIInsertHardClausesLegacy() : MachineFunctionPass(ID) {}
263+
264+
bool runOnMachineFunction(MachineFunction &MF) override {
265+
if (skipFunction(MF.getFunction()))
266+
return false;
267+
268+
return SIInsertHardClauses().run(MF);
269+
}
270+
271+
void getAnalysisUsage(AnalysisUsage &AU) const override {
272+
AU.setPreservesCFG();
273+
MachineFunctionPass::getAnalysisUsage(AU);
274+
}
275+
};
276+
268277
} // namespace
269278

270-
char SIInsertHardClauses::ID = 0;
279+
PreservedAnalyses
280+
llvm::SIInsertHardClausesPass::run(MachineFunction &MF,
281+
MachineFunctionAnalysisManager &MFAM) {
282+
if (!SIInsertHardClauses().run(MF))
283+
return PreservedAnalyses::all();
284+
285+
auto PA = getMachineFunctionPassPreservedAnalyses();
286+
PA.preserveSet<CFGAnalyses>();
287+
return PA;
288+
}
289+
290+
char SIInsertHardClausesLegacy::ID = 0;
271291

272-
char &llvm::SIInsertHardClausesID = SIInsertHardClauses::ID;
292+
char &llvm::SIInsertHardClausesID = SIInsertHardClausesLegacy::ID;
273293

274-
INITIALIZE_PASS(SIInsertHardClauses, DEBUG_TYPE, "SI Insert Hard Clauses",
294+
INITIALIZE_PASS(SIInsertHardClausesLegacy, DEBUG_TYPE, "SI Insert Hard Clauses",
275295
false, false)

llvm/test/CodeGen/AMDGPU/hard-clauses-img-gfx10.mir

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,6 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
22
# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs -run-pass si-insert-hard-clauses %s -o - | FileCheck %s
3+
# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs -passes si-insert-hard-clauses %s -o - | FileCheck %s
34

45
---
56
name: mimg_nsa

llvm/test/CodeGen/AMDGPU/hard-clauses-img-gfx11.mir

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,6 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
22
# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs -run-pass si-insert-hard-clauses %s -o - | FileCheck %s
3+
# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs -passes si-insert-hard-clauses %s -o - | FileCheck %s
34

45
---
56
name: mimg_nsa

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