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fixup! make sure we PrintFatalError
1 parent 9235b8d commit 3fc1d3e

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1 file changed

+22
-15
lines changed

1 file changed

+22
-15
lines changed

llvm/utils/TableGen/SubtargetEmitter.cpp

+22-15
Original file line numberDiff line numberDiff line change
@@ -902,17 +902,20 @@ SubtargetEmitter::FindWriteResources(const CodeGenSchedRW &SchedWrite,
902902
for (Record *WR : ProcModel.WriteResDefs) {
903903
if (!WR->isSubClassOf("WriteRes"))
904904
continue;
905-
if (AliasDef == WR->getValueAsDef("WriteType") ||
906-
SchedWrite.TheDef == WR->getValueAsDef("WriteType")) {
905+
// If there is no AliasDef and we find a match, we can early exit since
906+
// there is no need to verify whether there are resources defined for both
907+
// SchedWrite and its alias.
908+
if (!AliasDef && SchedWrite.TheDef == WR->getValueAsDef("WriteType")) {
907909
ResDef = WR;
908910
break;
909-
}
910-
}
911-
912-
if (ResDef && AliasDef) {
913-
PrintFatalError(ResDef->getLoc(), "Resources are defined for both "
911+
} else if (AliasDef == WR->getValueAsDef("WriteType")) {
912+
if (ResDef) {
913+
PrintFatalError(WR->getLoc(), "Resources are defined for both "
914914
"SchedWrite and its alias on processor " +
915915
ProcModel.ModelName);
916+
}
917+
ResDef = WR;
918+
}
916919
}
917920

918921
// TODO: If ProcModel has a base model (previous generation processor),
@@ -959,16 +962,20 @@ Record *SubtargetEmitter::FindReadAdvance(const CodeGenSchedRW &SchedRead,
959962
for (Record *RA : ProcModel.ReadAdvanceDefs) {
960963
if (!RA->isSubClassOf("ReadAdvance"))
961964
continue;
962-
if (AliasDef == RA->getValueAsDef("ReadType") ||
963-
SchedRead.TheDef == RA->getValueAsDef("ReadType")) {
964-
ResDef = RA;
965+
// If there is no AliasDef and we find a match, we can early exit since
966+
// there is no need to verify whether there are resources defined for both
967+
// SchedWrite and its alias.
968+
if (!AliasDef && AliasDef == RA->getValueAsDef("ReadType")) {
969+
ResDef = WR;
965970
break;
966-
}
967-
}
968-
if (ResDef && AliasDef) {
969-
PrintFatalError(ResDef->getLoc(), "Resources are defined for both "
970-
"SchedRead and its alias on processor " +
971+
} else if (SchedRead.TheDef == RA->getValueAsDef("ReadType")) {
972+
if (ResDef) {
973+
PrintFatalError(WR->getLoc(), "Resources are defined for both "
974+
"SchedWrite and its alias on processor " +
971975
ProcModel.ModelName);
976+
}
977+
ResDef = RA;
978+
}
972979
}
973980

974981
// TODO: If ProcModel has a base model (previous generation processor),

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