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[test] Fix check prefixes
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6 files changed

+54
-55
lines changed

6 files changed

+54
-55
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‎llvm/test/CodeGen/AArch64/aarch64_tree_tests.ll

+19-21
Original file line numberDiff line numberDiff line change
@@ -1,19 +1,18 @@
1-
; RUN: llc < %s | FileCheck %s
1+
; RUN: llc < %s | FileCheck %s
22

33
; ModuleID = 'aarch64_tree_tests.bc'
44
target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
55
target triple = "arm64--linux-gnu"
66

7-
; FIXME: Misspelled CHECK-LABEL
8-
; CHECK-LABLE: @aarch64_tree_tests_and
9-
; CHECK: .hword 32768
10-
; CHECK: .hword 32767
11-
; CHECK: .hword 4664
12-
; CHECK: .hword 32767
13-
; CHECK: .hword 32768
14-
; CHECK: .hword 32768
15-
; CHECK: .hword 0
16-
; CHECK: .hword 0
7+
; CHECK-LABEL: .LCPI0_0:
8+
; CHECK-NEXT: .hword 32768
9+
; CHECK-NEXT: .hword 32767
10+
; CHECK-NEXT: .hword 4664
11+
; CHECK-NEXT: .hword 32767
12+
; CHECK-NEXT: .hword 32768
13+
; CHECK-NEXT: .hword 32768
14+
; CHECK-NEXT: .hword 0
15+
; CHECK-NEXT: .hword 0
1716

1817
; Function Attrs: nounwind readnone
1918
define <8 x i16> @aarch64_tree_tests_and(<8 x i16> %a) {
@@ -23,16 +22,15 @@ entry:
2322
ret <8 x i16> %ret
2423
}
2524

26-
; FIXME: Misspelled CHECK-LABEL
27-
; CHECK-LABLE: @aarch64_tree_tests_or
28-
; CHECK: .hword 32768
29-
; CHECK: .hword 32766
30-
; CHECK: .hword 4664
31-
; CHECK: .hword 32766
32-
; CHECK: .hword 32768
33-
; CHECK: .hword 32768
34-
; CHECK: .hword 65535
35-
; CHECK: .hword 65535
25+
; CHECK-LABEL: .LCPI1_0:
26+
; CHECK-NEXT: .hword 32768
27+
; CHECK-NEXT: .hword 32766
28+
; CHECK-NEXT: .hword 4664
29+
; CHECK-NEXT: .hword 32766
30+
; CHECK-NEXT: .hword 32768
31+
; CHECK-NEXT: .hword 32768
32+
; CHECK-NEXT: .hword 65535
33+
; CHECK-NEXT: .hword 65535
3634

3735
; Function Attrs: nounwind readnone
3836
define <8 x i16> @aarch64_tree_tests_or(<8 x i16> %a) {

‎llvm/test/CodeGen/SPARC/inlineasm-bad.ll

+2-3
Original file line numberDiff line numberDiff line change
@@ -12,9 +12,8 @@ entry:
1212
ret void
1313
}
1414

15-
; CHECK-label:test_twinword_error
16-
; CHECK: error: Hi part of pair should point to an even-numbered register
17-
; CHECK: error: (note that in some cases it might be necessary to manually bind the input/output registers instead of relying on automatic allocation)
15+
; CHECK: <unknown>:0: error: Hi part of pair should point to an even-numbered register
16+
; CHECK: <unknown>:0: error: (note that in some cases it might be necessary to manually bind the input/output registers instead of relying on automatic allocation)
1817

1918
define i64 @test_twinword_error(){
2019
%1 = tail call i64 asm sideeffect "rd %asr5, ${0:L} \0A\09 srlx ${0:L}, 32, ${0:H}", "={i1}"()

‎llvm/test/MC/AArch64/SVE/index.s

+8-8
Original file line numberDiff line numberDiff line change
@@ -180,16 +180,16 @@ index z21.b, w10, w21
180180
// CHECK-UNKNOWN: 04354d55 <unknown>
181181

182182
index z31.h, wzr, wzr
183-
// check-inst: index z31.h, wzr, wzr
184-
// check-encoding: [0xff,0x4f,0x7f,0x04]
185-
// check-error: instruction requires: sve or sme
186-
// check-unknown: ff 4f 7f 04 <unknown>
183+
// CHECK-INST: index z31.h, wzr, wzr
184+
// CHECK-ENCODING: [0xff,0x4f,0x7f,0x04]
185+
// CHECK-ERROR: instruction requires: sve or sme
186+
// CHECK-UNKNOWN: 047f4fff <unknown>
187187

188188
index z0.h, w0, w0
189-
// check-inst: index z0.h, w0, w0
190-
// check-encoding: [0x00,0x4c,0x60,0x04]
191-
// check-error: instruction requires: sve or sme
192-
// check-unknown: 00 4c 60 04 <unknown>
189+
// CHECK-INST: index z0.h, w0, w0
190+
// CHECK-ENCODING: [0x00,0x4c,0x60,0x04]
191+
// CHECK-ERROR: instruction requires: sve or sme
192+
// CHECK-UNKNOWN: 04604c00 <unknown>
193193

194194
index z31.s, wzr, wzr
195195
// CHECK-INST: index z31.s, wzr, wzr

‎llvm/test/MC/XCOFF/inlineasm.s

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// RUN: llvm-mc -filetype=asm -triple powerpc-ibm-aix-xcoff %s | FileCheck %s
22

3-
// CHECK-label: .csect .text[PR],2
3+
// CHECK-LABEL: .csect ..text..[PR],5
44
// CHECK:L..tmp0:
55
// CHECK-NEXT: lwarx 3, 0, 4
66
// CHECK-NEXT: cmpw 5, 3

‎llvm/test/Transforms/PhaseOrdering/lifetime-sanitizer.ll

+11-9
Original file line numberDiff line numberDiff line change
@@ -1,11 +1,11 @@
1-
; RUN: opt < %s -O0 -S | FileCheck %s
2-
; RUN: opt < %s -O1 -S | FileCheck %s
3-
; RUN: opt < %s -O2 -S | FileCheck %s
4-
; RUN: opt < %s -O3 -S | FileCheck %s
5-
; RUN: opt < %s -passes='default<O0>' -S | FileCheck %s
6-
; RUN: opt < %s -passes='default<O1>' -S | FileCheck %s
7-
; RUN: opt < %s -passes='default<O2>' -S | FileCheck %s
8-
; RUN: opt < %s -passes='default<O3>' -S | FileCheck %s
1+
; RUN: opt < %s -O0 -S | FileCheck %s --check-prefixes=CHECK,NOOPT
2+
; RUN: opt < %s -O1 -S | FileCheck %s --check-prefixes=CHECK,OPT
3+
; RUN: opt < %s -O2 -S | FileCheck %s --check-prefixes=CHECK,OPT
4+
; RUN: opt < %s -O3 -S | FileCheck %s --check-prefixes=CHECK,OPT
5+
; RUN: opt < %s -passes='default<O0>' -S | FileCheck %s --check-prefixes=CHECK,NOOPT
6+
; RUN: opt < %s -passes='default<O1>' -S | FileCheck %s --check-prefixes=CHECK,OPT
7+
; RUN: opt < %s -passes='default<O2>' -S | FileCheck %s --check-prefixes=CHECK,OPT
8+
; RUN: opt < %s -passes='default<O3>' -S | FileCheck %s --check-prefixes=CHECK,OPT
99

1010
declare void @llvm.lifetime.start.p0(i64, ptr nocapture)
1111
declare void @llvm.lifetime.end.p0(i64, ptr nocapture)
@@ -63,7 +63,9 @@ entry:
6363

6464
call void @llvm.lifetime.start.p0(i64 1, ptr %text)
6565
call void @llvm.lifetime.end.p0(i64 1, ptr %text)
66-
; CHECK-NO: call void @llvm.lifetime
66+
; OPT-NOT: call void @llvm.lifetime
67+
; NOOPT: call void @llvm.lifetime.start
68+
; NOOPT-NEXT: call void @llvm.lifetime.end
6769

6870
call void @foo(ptr %text) ; Keep alloca alive
6971

‎llvm/test/tools/dsymutil/ARM/dwarf5-macho.test

+13-13
Original file line numberDiff line numberDiff line change
@@ -109,16 +109,16 @@ CHECK-NEXT: 0x0000000e: [DW_RLE_offset_pair ]: {{.*}}[0x[[RANGELIST_OFFSET_STAR
109109
CHECK-NEXT: 0x00000011: [DW_RLE_end_of_list ]
110110

111111
CHECK: .debug_names contents:
112-
CHECK-NEX:T Name Index @ 0x0 {
113-
CHECK-NEX:T Header {
114-
CHECK-NEX:T Length: 0x7C
115-
CHECK-NEX:T Format: DWARF32
116-
CHECK-NEX:T Version: 5
117-
CHECK-NEX:T CU count: 1
118-
CHECK-NEX:T Local TU count: 0
119-
CHECK-NEX:T Foreign TU count: 0
120-
CHECK-NEX:T Bucket count: 3
121-
CHECK-NEX:T Name count: 3
122-
CHECK-NEX:T Abbreviations table size: 0xD
123-
CHECK-NEX:T Augmentation: 'LLVM0700'
124-
CHECK-NEX:T }
112+
CHECK-NEXT: Name Index @ 0x0 {
113+
CHECK-NEXT: Header {
114+
CHECK-NEXT: Length:
115+
CHECK-NEXT: Format: DWARF32
116+
CHECK-NEXT: Version: 5
117+
CHECK-NEXT: CU count: 1
118+
CHECK-NEXT: Local TU count: 0
119+
CHECK-NEXT: Foreign TU count: 0
120+
CHECK-NEXT: Bucket count: 3
121+
CHECK-NEXT: Name count: 3
122+
CHECK-NEXT: Abbreviations table size:
123+
CHECK-NEXT: Augmentation: 'LLVM0700'
124+
CHECK-NEXT: }

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