@@ -105,22 +105,63 @@ defm AMOMAXU_D : AMO_rr_aq_rl<0b11100, 0b011, "amomaxu.d">,
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// Pseudo-instructions and codegen patterns
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//===----------------------------------------------------------------------===//
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+ // An atomic load operation that does not need either acquire or release
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+ // semantics.
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+ class relaxed_load<PatFrags base>
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+ : PatFrag<(ops node:$ptr), (base node:$ptr)> {
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+ let IsAtomic = 1;
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+ let IsAtomicOrderingMonotonic = 1;
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+ }
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+
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+ // A atomic load operation that actually needs acquire semantics.
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+ class acquiring_load<PatFrags base>
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+ : PatFrag<(ops node:$ptr), (base node:$ptr)> {
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+ let IsAtomic = 1;
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+ let IsAtomicOrderingAcquire = 1;
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+ }
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+
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+ // An atomic load operation that needs sequential consistency.
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+ class seq_cst_load<PatFrags base>
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+ : PatFrag<(ops node:$ptr), (base node:$ptr)> {
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+ let IsAtomic = 1;
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+ let IsAtomicOrderingSequentiallyConsistent = 1;
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+ }
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+
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+ // An atomic store operation that doesn't actually need to be atomic on RISCV.
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+ class relaxed_store<PatFrag base>
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+ : PatFrag<(ops node:$ptr, node:$val), (base node:$val, node:$ptr)> {
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+ let IsAtomic = 1;
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+ let IsAtomicOrderingMonotonic = 1;
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+ }
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+
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+ // A store operation that actually needs release semantics.
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+ class releasing_store<PatFrag base>
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+ : PatFrag<(ops node:$ptr, node:$val), (base node:$val, node:$ptr)> {
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+ let IsAtomic = 1;
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+ let IsAtomicOrderingRelease = 1;
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+ }
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+
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+ // A store operation that actually needs sequential consistency.
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+ class seq_cst_store<PatFrag base>
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+ : PatFrag<(ops node:$ptr, node:$val), (base node:$val, node:$ptr)> {
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+ let IsAtomic = 1;
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+ let IsAtomicOrderingSequentiallyConsistent = 1;
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+ }
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+
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// Atomic load/store are available under both +a and +force-atomics.
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- // Fences will be inserted for atomic load/stores according to the logic in
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- // RISCVTargetLowering::{emitLeadingFence,emitTrailingFence}.
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let Predicates = [HasAtomicLdSt] in {
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- def : LdPat<atomic_load_8, LB>;
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- def : LdPat<atomic_load_16, LH>;
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- def : LdPat<atomic_load_32, LW>;
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+ def : LdPat<relaxed_load< atomic_load_8> , LB>;
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+ def : LdPat<relaxed_load< atomic_load_16> , LH>;
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+ def : LdPat<relaxed_load< atomic_load_32> , LW>;
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- def : StPat<atomic_store_8, SB, GPR, XLenVT>;
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- def : StPat<atomic_store_16, SH, GPR, XLenVT>;
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- def : StPat<atomic_store_32, SW, GPR, XLenVT>;
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+ def : StPat<relaxed_store< atomic_store_8> , SB, GPR, XLenVT>;
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+ def : StPat<relaxed_store< atomic_store_16> , SH, GPR, XLenVT>;
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+ def : StPat<relaxed_store< atomic_store_32> , SW, GPR, XLenVT>;
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}
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let Predicates = [HasAtomicLdSt, IsRV64] in {
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- def : LdPat<atomic_load_64, LD, i64>;
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- def : StPat<atomic_store_64, SD, GPR, i64>;
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+ def : LdPat<relaxed_load< atomic_load_64> , LD, i64>;
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+ def : StPat<relaxed_store< atomic_store_64> , SD, GPR, i64>;
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}
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/// AMOs
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