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Commit 5cd0279

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author
Brendan Sweeney
committed
Adding isel lowering for Zalasr. Not sure if is matches the psABI yet though
1 parent c5ade18 commit 5cd0279

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4 files changed

+94
-14
lines changed

4 files changed

+94
-14
lines changed

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -20506,6 +20506,14 @@ unsigned RISCVTargetLowering::getCustomCtpopCost(EVT VT,
2050620506
return isCtpopFast(VT) ? 0 : 1;
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}
2050820508

20509+
bool RISCVTargetLowering::shouldInsertFencesForAtomic(const Instruction *I) const {
20510+
if (Subtarget.hasStdExtZalasr()) {
20511+
return false;
20512+
} else {
20513+
return isa<LoadInst>(I) || isa<StoreInst>(I);
20514+
}
20515+
}
20516+
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bool RISCVTargetLowering::fallBackToDAGISel(const Instruction &Inst) const {
2051020518

2051120519
// GISel support is in progress or complete for G_ADD, G_SUB, G_AND, G_OR, and

llvm/lib/Target/RISCV/RISCVISelLowering.h

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -689,9 +689,8 @@ class RISCVTargetLowering : public TargetLowering {
689689

690690
bool preferZeroCompareBranch() const override { return true; }
691691

692-
bool shouldInsertFencesForAtomic(const Instruction *I) const override {
693-
return isa<LoadInst>(I) || isa<StoreInst>(I);
694-
}
692+
bool shouldInsertFencesForAtomic(const Instruction *I) const override;
693+
695694
Instruction *emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst,
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AtomicOrdering Ord) const override;
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Instruction *emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst,

llvm/lib/Target/RISCV/RISCVInstrInfoA.td

Lines changed: 51 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -105,22 +105,63 @@ defm AMOMAXU_D : AMO_rr_aq_rl<0b11100, 0b011, "amomaxu.d">,
105105
// Pseudo-instructions and codegen patterns
106106
//===----------------------------------------------------------------------===//
107107

108+
// An atomic load operation that does not need either acquire or release
109+
// semantics.
110+
class relaxed_load<PatFrags base>
111+
: PatFrag<(ops node:$ptr), (base node:$ptr)> {
112+
let IsAtomic = 1;
113+
let IsAtomicOrderingMonotonic = 1;
114+
}
115+
116+
// A atomic load operation that actually needs acquire semantics.
117+
class acquiring_load<PatFrags base>
118+
: PatFrag<(ops node:$ptr), (base node:$ptr)> {
119+
let IsAtomic = 1;
120+
let IsAtomicOrderingAcquire = 1;
121+
}
122+
123+
// An atomic load operation that needs sequential consistency.
124+
class seq_cst_load<PatFrags base>
125+
: PatFrag<(ops node:$ptr), (base node:$ptr)> {
126+
let IsAtomic = 1;
127+
let IsAtomicOrderingSequentiallyConsistent = 1;
128+
}
129+
130+
// An atomic store operation that doesn't actually need to be atomic on RISCV.
131+
class relaxed_store<PatFrag base>
132+
: PatFrag<(ops node:$ptr, node:$val), (base node:$val, node:$ptr)> {
133+
let IsAtomic = 1;
134+
let IsAtomicOrderingMonotonic = 1;
135+
}
136+
137+
// A store operation that actually needs release semantics.
138+
class releasing_store<PatFrag base>
139+
: PatFrag<(ops node:$ptr, node:$val), (base node:$val, node:$ptr)> {
140+
let IsAtomic = 1;
141+
let IsAtomicOrderingRelease = 1;
142+
}
143+
144+
// A store operation that actually needs sequential consistency.
145+
class seq_cst_store<PatFrag base>
146+
: PatFrag<(ops node:$ptr, node:$val), (base node:$val, node:$ptr)> {
147+
let IsAtomic = 1;
148+
let IsAtomicOrderingSequentiallyConsistent = 1;
149+
}
150+
108151
// Atomic load/store are available under both +a and +force-atomics.
109-
// Fences will be inserted for atomic load/stores according to the logic in
110-
// RISCVTargetLowering::{emitLeadingFence,emitTrailingFence}.
111152
let Predicates = [HasAtomicLdSt] in {
112-
def : LdPat<atomic_load_8, LB>;
113-
def : LdPat<atomic_load_16, LH>;
114-
def : LdPat<atomic_load_32, LW>;
153+
def : LdPat<relaxed_load<atomic_load_8>, LB>;
154+
def : LdPat<relaxed_load<atomic_load_16>, LH>;
155+
def : LdPat<relaxed_load<atomic_load_32>, LW>;
115156

116-
def : StPat<atomic_store_8, SB, GPR, XLenVT>;
117-
def : StPat<atomic_store_16, SH, GPR, XLenVT>;
118-
def : StPat<atomic_store_32, SW, GPR, XLenVT>;
157+
def : StPat<relaxed_store<atomic_store_8>, SB, GPR, XLenVT>;
158+
def : StPat<relaxed_store<atomic_store_16>, SH, GPR, XLenVT>;
159+
def : StPat<relaxed_store<atomic_store_32>, SW, GPR, XLenVT>;
119160
}
120161

121162
let Predicates = [HasAtomicLdSt, IsRV64] in {
122-
def : LdPat<atomic_load_64, LD, i64>;
123-
def : StPat<atomic_store_64, SD, GPR, i64>;
163+
def : LdPat<relaxed_load<atomic_load_64>, LD, i64>;
164+
def : StPat<relaxed_store<atomic_store_64>, SD, GPR, i64>;
124165
}
125166

126167
/// AMOs

llvm/lib/Target/RISCV/RISCVInstrInfoZalasr.td

Lines changed: 33 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -63,4 +63,36 @@ defm SD_RL : SRL_r_aq_rl<0b011, "sd">;
6363
// Pseudo-instructions and codegen patterns
6464
//===----------------------------------------------------------------------===//
6565

66-
// Future work: Work out mapping with leading/trailing fences, &c
66+
class PatLAQ<SDPatternOperator OpNode, RVInst Inst, ValueType vt = XLenVT>
67+
: Pat<(vt (OpNode (vt GPRMemZeroOffset:$rs1))), (Inst GPRMemZeroOffset:$rs1)>;
68+
69+
class PatSRL<SDPatternOperator OpNode, RVInst Inst, ValueType vt = XLenVT>
70+
: Pat<(OpNode (vt GPR:$rs2), (vt GPRMemZeroOffset:$rs1)), (Inst GPR:$rs2, GPRMemZeroOffset:$rs1)>;
71+
72+
let Predicates = [HasStdExtZalasr] in {
73+
def : PatLAQ<acquiring_load<atomic_load_8>, LB_AQ_AQ>;
74+
def : PatLAQ<seq_cst_load<atomic_load_8>, LB_AQ_AQ_RL>;
75+
76+
def : PatLAQ<acquiring_load<atomic_load_16>, LH_AQ_AQ>;
77+
def : PatLAQ<seq_cst_load<atomic_load_16>, LH_AQ_AQ_RL>;
78+
79+
def : PatLAQ<acquiring_load<atomic_load_32>, LW_AQ_AQ>;
80+
def : PatLAQ<seq_cst_load<atomic_load_32>, LW_AQ_AQ_RL>;
81+
82+
def : PatSRL<releasing_store<atomic_store_8>, SB_RL_RL>;
83+
def : PatSRL<seq_cst_store<atomic_store_8>, SB_RL_AQ_RL>;
84+
85+
def : PatSRL<releasing_store<atomic_store_16>, SH_RL_RL>;
86+
def : PatSRL<seq_cst_store<atomic_store_16>, SH_RL_AQ_RL>;
87+
88+
def : PatSRL<releasing_store<atomic_store_32>, SW_RL_RL>;
89+
def : PatSRL<seq_cst_store<atomic_store_32>, SW_RL_AQ_RL>;
90+
} // Predicates HasStdExtZalasr
91+
92+
let Predicates = [HasStdExtZalasr, IsRV64] in {
93+
def : PatLAQ<acquiring_load<atomic_load_64>, LD_AQ_AQ>;
94+
def : PatLAQ<seq_cst_load<atomic_load_64>, LD_AQ_AQ_RL>;
95+
96+
def : PatSRL<releasing_store<atomic_store_64>, SD_RL_RL>;
97+
def : PatSRL<seq_cst_store<atomic_store_64>, SD_RL_AQ_RL>;
98+
} // Predicates HasStdExtZalasr, IsRV64

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