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[WebAssembly] Prototype extending pairwise add instructions
As proposed in WebAssembly/simd#380. This commit makes the new instructions available only via clang builtins and LLVM intrinsics to make their use opt-in while they are still being evaluated for inclusion in the SIMD proposal. Depends on D93771. Differential Revision: https://reviews.llvm.org/D93775
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‎clang/include/clang/Basic/BuiltinsWebAssembly.def

+6
Original file line numberDiff line numberDiff line change
@@ -133,6 +133,12 @@ TARGET_BUILTIN(__builtin_wasm_extmul_high_i32x4_s_i64x2, "V2LLiV4iV4i", "nc", "s
133133
TARGET_BUILTIN(__builtin_wasm_extmul_low_i32x4_u_i64x2, "V2ULLiV4UiV4Ui", "nc", "simd128")
134134
TARGET_BUILTIN(__builtin_wasm_extmul_high_i32x4_u_i64x2, "V2ULLiV4UiV4Ui", "nc", "simd128")
135135

136+
TARGET_BUILTIN(__builtin_wasm_extadd_pairwise_i8x16_s_i16x8, "V8sV16Sc", "nc", "simd128")
137+
TARGET_BUILTIN(__builtin_wasm_extadd_pairwise_i8x16_u_i16x8, "V8UsV16Uc", "nc", "simd128")
138+
139+
TARGET_BUILTIN(__builtin_wasm_extadd_pairwise_i16x8_s_i32x4, "V4iV8s", "nc", "simd128")
140+
TARGET_BUILTIN(__builtin_wasm_extadd_pairwise_i16x8_u_i32x4, "V4UiV8Us", "nc", "simd128")
141+
136142
TARGET_BUILTIN(__builtin_wasm_bitselect, "V4iV4iV4iV4i", "nc", "simd128")
137143

138144
TARGET_BUILTIN(__builtin_wasm_signselect_i8x16, "V16ScV16ScV16ScV16Sc", "nc", "simd128")

‎clang/lib/CodeGen/CGBuiltin.cpp

+22
Original file line numberDiff line numberDiff line change
@@ -16932,6 +16932,28 @@ Value *CodeGenFunction::EmitWebAssemblyBuiltinExpr(unsigned BuiltinID,
1693216932
Function *Callee = CGM.getIntrinsic(IntNo, ConvertType(E->getType()));
1693316933
return Builder.CreateCall(Callee, {LHS, RHS});
1693416934
}
16935+
case WebAssembly::BI__builtin_wasm_extadd_pairwise_i8x16_s_i16x8:
16936+
case WebAssembly::BI__builtin_wasm_extadd_pairwise_i8x16_u_i16x8:
16937+
case WebAssembly::BI__builtin_wasm_extadd_pairwise_i16x8_s_i32x4:
16938+
case WebAssembly::BI__builtin_wasm_extadd_pairwise_i16x8_u_i32x4: {
16939+
Value *Vec = EmitScalarExpr(E->getArg(0));
16940+
unsigned IntNo;
16941+
switch (BuiltinID) {
16942+
case WebAssembly::BI__builtin_wasm_extadd_pairwise_i8x16_s_i16x8:
16943+
case WebAssembly::BI__builtin_wasm_extadd_pairwise_i16x8_s_i32x4:
16944+
IntNo = Intrinsic::wasm_extadd_pairwise_signed;
16945+
break;
16946+
case WebAssembly::BI__builtin_wasm_extadd_pairwise_i8x16_u_i16x8:
16947+
case WebAssembly::BI__builtin_wasm_extadd_pairwise_i16x8_u_i32x4:
16948+
IntNo = Intrinsic::wasm_extadd_pairwise_unsigned;
16949+
break;
16950+
default:
16951+
llvm_unreachable("unexptected builtin ID");
16952+
}
16953+
16954+
Function *Callee = CGM.getIntrinsic(IntNo, ConvertType(E->getType()));
16955+
return Builder.CreateCall(Callee, Vec);
16956+
}
1693516957
case WebAssembly::BI__builtin_wasm_bitselect: {
1693616958
Value *V1 = EmitScalarExpr(E->getArg(0));
1693716959
Value *V2 = EmitScalarExpr(E->getArg(1));

‎clang/test/CodeGen/builtins-wasm.c

+28
Original file line numberDiff line numberDiff line change
@@ -603,6 +603,34 @@ u64x2 extmul_high_i32x4_u_i64x2(u32x4 x, u32x4 y) {
603603
// WEBASSEMBLY-NEXT: ret
604604
}
605605

606+
i16x8 extadd_pairwise_i8x16_s_i16x8(i8x16 v) {
607+
return __builtin_wasm_extadd_pairwise_i8x16_s_i16x8(v);
608+
// WEBASSEMBLY: call <8 x i16> @llvm.wasm.extadd.pairwise.signed.v8i16(
609+
// WEBASSEMBLY-SAME: <16 x i8> %v)
610+
// WEBASSEMBLY-NEXT: ret
611+
}
612+
613+
u16x8 extadd_pairwise_i8x16_u_i16x8(u8x16 v) {
614+
return __builtin_wasm_extadd_pairwise_i8x16_u_i16x8(v);
615+
// WEBASSEMBLY: call <8 x i16> @llvm.wasm.extadd.pairwise.unsigned.v8i16(
616+
// WEBASSEMBLY-SAME: <16 x i8> %v)
617+
// WEBASSEMBLY-NEXT: ret
618+
}
619+
620+
i32x4 extadd_pairwise_i16x8_s_i32x4(i16x8 v) {
621+
return __builtin_wasm_extadd_pairwise_i16x8_s_i32x4(v);
622+
// WEBASSEMBLY: call <4 x i32> @llvm.wasm.extadd.pairwise.signed.v4i32(
623+
// WEBASSEMBLY-SAME: <8 x i16> %v)
624+
// WEBASSEMBLY-NEXT: ret
625+
}
626+
627+
u32x4 extadd_pairwise_i16x8_u_i32x4(u16x8 v) {
628+
return __builtin_wasm_extadd_pairwise_i16x8_u_i32x4(v);
629+
// WEBASSEMBLY: call <4 x i32> @llvm.wasm.extadd.pairwise.unsigned.v4i32(
630+
// WEBASSEMBLY-SAME: <8 x i16> %v)
631+
// WEBASSEMBLY-NEXT: ret
632+
}
633+
606634
i32x4 dot_i16x8_s(i16x8 x, i16x8 y) {
607635
return __builtin_wasm_dot_s_i32x4_i16x8(x, y);
608636
// WEBASSEMBLY: call <4 x i32> @llvm.wasm.dot(<8 x i16> %x, <8 x i16> %y)

‎llvm/include/llvm/IR/IntrinsicsWebAssembly.td

+9
Original file line numberDiff line numberDiff line change
@@ -290,6 +290,15 @@ def int_wasm_extmul_high_unsigned :
290290
[LLVMSubdivide2VectorType<0>, LLVMSubdivide2VectorType<0>],
291291
[IntrNoMem, IntrSpeculatable]>;
292292

293+
def int_wasm_extadd_pairwise_signed :
294+
Intrinsic<[llvm_anyvector_ty],
295+
[LLVMSubdivide2VectorType<0>],
296+
[IntrNoMem, IntrSpeculatable]>;
297+
def int_wasm_extadd_pairwise_unsigned :
298+
Intrinsic<[llvm_anyvector_ty],
299+
[LLVMSubdivide2VectorType<0>],
300+
[IntrNoMem, IntrSpeculatable]>;
301+
293302
def int_wasm_signselect :
294303
Intrinsic<[llvm_anyvector_ty],
295304
[LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],

‎llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

+11
Original file line numberDiff line numberDiff line change
@@ -1246,6 +1246,17 @@ foreach t2 = !foldl(
12461246
) in
12471247
def : Pat<(t1 (bitconvert (t2 V128:$v))), (t1 V128:$v)>;
12481248

1249+
// Extended pairwise addition
1250+
defm "" : SIMDConvert<I16x8, I8x16, int_wasm_extadd_pairwise_signed,
1251+
"extadd_pairwise_i8x16_s", 0xc2>;
1252+
defm "" : SIMDConvert<I16x8, I8x16, int_wasm_extadd_pairwise_unsigned,
1253+
"extadd_pairwise_i8x16_u", 0xc3>;
1254+
defm "" : SIMDConvert<I32x4, I16x8, int_wasm_extadd_pairwise_signed,
1255+
"extadd_pairwise_i16x8_s", 0xa5>;
1256+
defm "" : SIMDConvert<I32x4, I16x8, int_wasm_extadd_pairwise_unsigned,
1257+
"extadd_pairwise_i16x8_u", 0xa6>;
1258+
1259+
12491260
//===----------------------------------------------------------------------===//
12501261
// Quasi-Fused Multiply- Add and Subtract (QFMA/QFMS)
12511262
//===----------------------------------------------------------------------===//

‎llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll

+41
Original file line numberDiff line numberDiff line change
@@ -309,6 +309,26 @@ define <8 x i16> @extmul_high_u_v8i16(<16 x i8> %x, <16 x i8> %y) {
309309
ret <8 x i16> %a
310310
}
311311

312+
; CHECK-LABEL: extadd_pairwise_s_v8i16:
313+
; SIMD128-NEXT: .functype extadd_pairwise_s_v8i16 (v128) -> (v128){{$}}
314+
; SIMD128-NEXT: i16x8.extadd_pairwise_i8x16_s $push[[R:[0-9]+]]=, $0{{$}}
315+
; SIMD128-NEXT: return $pop[[R]]{{$}}
316+
declare <8 x i16> @llvm.wasm.extadd.pairwise.signed.v8i16(<16 x i8>)
317+
define <8 x i16> @extadd_pairwise_s_v8i16(<16 x i8> %x) {
318+
%a = call <8 x i16> @llvm.wasm.extadd.pairwise.signed.v8i16(<16 x i8> %x)
319+
ret <8 x i16> %a
320+
}
321+
322+
; CHECK-LABEL: extadd_pairwise_u_v8i16:
323+
; SIMD128-NEXT: .functype extadd_pairwise_u_v8i16 (v128) -> (v128){{$}}
324+
; SIMD128-NEXT: i16x8.extadd_pairwise_i8x16_u $push[[R:[0-9]+]]=, $0{{$}}
325+
; SIMD128-NEXT: return $pop[[R]]{{$}}
326+
declare <8 x i16> @llvm.wasm.extadd.pairwise.unsigned.v8i16(<16 x i8>)
327+
define <8 x i16> @extadd_pairwise_u_v8i16(<16 x i8> %x) {
328+
%a = call <8 x i16> @llvm.wasm.extadd.pairwise.unsigned.v8i16(<16 x i8> %x)
329+
ret <8 x i16> %a
330+
}
331+
312332
; CHECK-LABEL: any_v8i16:
313333
; SIMD128-NEXT: .functype any_v8i16 (v128) -> (i32){{$}}
314334
; SIMD128-NEXT: i16x8.any_true $push[[R:[0-9]+]]=, $0{{$}}
@@ -449,6 +469,27 @@ define <4 x i32> @extmul_high_u_v4i32(<8 x i16> %x, <8 x i16> %y) {
449469
ret <4 x i32> %a
450470
}
451471

472+
; CHECK-LABEL: extadd_pairwise_s_v4i32:
473+
; SIMD128-NEXT: .functype extadd_pairwise_s_v4i32 (v128) -> (v128){{$}}
474+
; SIMD128-NEXT: i32x4.extadd_pairwise_i16x8_s $push[[R:[0-9]+]]=, $0{{$}}
475+
; SIMD128-NEXT: return $pop[[R]]{{$}}
476+
declare <4 x i32> @llvm.wasm.extadd.pairwise.signed.v4i32(<8 x i16>)
477+
define <4 x i32> @extadd_pairwise_s_v4i32(<8 x i16> %x) {
478+
%a = call <4 x i32> @llvm.wasm.extadd.pairwise.signed.v4i32(<8 x i16> %x)
479+
ret <4 x i32> %a
480+
}
481+
482+
; CHECK-LABEL: extadd_pairwise_u_v4i32:
483+
; SIMD128-NEXT: .functype extadd_pairwise_u_v4i32 (v128) -> (v128){{$}}
484+
; SIMD128-NEXT: i32x4.extadd_pairwise_i16x8_u $push[[R:[0-9]+]]=, $0{{$}}
485+
; SIMD128-NEXT: return $pop[[R]]{{$}}
486+
declare <4 x i32> @llvm.wasm.extadd.pairwise.unsigned.v4i32(<8 x i16>)
487+
define <4 x i32> @extadd_pairwise_u_v4i32(<8 x i16> %x) {
488+
%a = call <4 x i32> @llvm.wasm.extadd.pairwise.unsigned.v4i32(<8 x i16> %x)
489+
ret <4 x i32> %a
490+
}
491+
492+
452493
; CHECK-LABEL: any_v4i32:
453494
; SIMD128-NEXT: .functype any_v4i32 (v128) -> (i32){{$}}
454495
; SIMD128-NEXT: i32x4.any_true $push[[R:[0-9]+]]=, $0{{$}}

‎llvm/test/MC/WebAssembly/simd-encodings.s

+12
Original file line numberDiff line numberDiff line change
@@ -724,4 +724,16 @@ main:
724724
# CHECK: i64x2.signselect # encoding: [0xfd,0x94,0x01]
725725
i64x2.signselect
726726

727+
# CHECK: i16x8.extadd_pairwise_i8x16_s # encoding: [0xfd,0xc2,0x01]
728+
i16x8.extadd_pairwise_i8x16_s
729+
730+
# CHECK: i16x8.extadd_pairwise_i8x16_u # encoding: [0xfd,0xc3,0x01]
731+
i16x8.extadd_pairwise_i8x16_u
732+
733+
# CHECK: i32x4.extadd_pairwise_i16x8_s # encoding: [0xfd,0xa5,0x01]
734+
i32x4.extadd_pairwise_i16x8_s
735+
736+
# CHECK: i32x4.extadd_pairwise_i16x8_u # encoding: [0xfd,0xa6,0x01]
737+
i32x4.extadd_pairwise_i16x8_u
738+
727739
end_function

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