Skip to content

Commit 63fae3e

Browse files
jayfoadjayfoad
authored
[AMDGPU] clang-tidy: no else after return etc. NFC. (#99298)
1 parent 495d3ea commit 63fae3e

24 files changed

+273
-304
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1450,7 +1450,8 @@ bool AMDGPUAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
14501450
AMDGPUInstPrinter::printRegOperand(MO.getReg(), O,
14511451
*MF->getSubtarget().getRegisterInfo());
14521452
return false;
1453-
} else if (MO.isImm()) {
1453+
}
1454+
if (MO.isImm()) {
14541455
int64_t Val = MO.getImm();
14551456
if (AMDGPU::isInlinableIntLiteral(Val)) {
14561457
O << Val;

‎llvm/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp

Lines changed: 61 additions & 68 deletions
Original file line numberDiff line numberDiff line change
@@ -568,16 +568,14 @@ class RegionMRT : public MRT {
568568
bool contains(MachineBasicBlock *MBB) {
569569
for (auto *CI : Children) {
570570
if (CI->isMBB()) {
571-
if (MBB == CI->getMBBMRT()->getMBB()) {
571+
if (MBB == CI->getMBBMRT()->getMBB())
572572
return true;
573-
}
574573
} else {
575-
if (CI->getRegionMRT()->contains(MBB)) {
574+
if (CI->getRegionMRT()->contains(MBB))
576575
return true;
577-
} else if (CI->getRegionMRT()->getLinearizedRegion() != nullptr &&
578-
CI->getRegionMRT()->getLinearizedRegion()->contains(MBB)) {
576+
if (CI->getRegionMRT()->getLinearizedRegion() != nullptr &&
577+
CI->getRegionMRT()->getLinearizedRegion()->contains(MBB))
579578
return true;
580-
}
581579
}
582580
}
583581
return false;
@@ -2259,63 +2257,60 @@ MachineBasicBlock *AMDGPUMachineCFGStructurizer::createIfRegion(
22592257
CodeBB->addSuccessor(MergeBB);
22602258
CurrentRegion->addMBB(CodeBB);
22612259
return nullptr;
2262-
} else {
2263-
// Handle internal block.
2264-
const TargetRegisterClass *RegClass = MRI->getRegClass(BBSelectRegIn);
2265-
Register CodeBBSelectReg = MRI->createVirtualRegister(RegClass);
2266-
rewriteCodeBBTerminator(CodeBB, MergeBB, CodeBBSelectReg);
2267-
bool IsRegionEntryBB = CurrentRegion->getEntry() == CodeBB;
2268-
MachineBasicBlock *IfBB = createIfBlock(MergeBB, CodeBB, CodeBB, CodeBB,
2269-
BBSelectRegIn, IsRegionEntryBB);
2270-
CurrentRegion->addMBB(IfBB);
2271-
// If this is the entry block we need to make the If block the new
2272-
// linearized region entry.
2273-
if (IsRegionEntryBB) {
2274-
CurrentRegion->setEntry(IfBB);
2275-
2276-
if (CurrentRegion->getHasLoop()) {
2277-
MachineBasicBlock *RegionExit = CurrentRegion->getExit();
2278-
MachineBasicBlock *ETrueBB = nullptr;
2279-
MachineBasicBlock *EFalseBB = nullptr;
2280-
SmallVector<MachineOperand, 1> ECond;
2281-
2282-
const DebugLoc &DL = DebugLoc();
2283-
TII->analyzeBranch(*RegionExit, ETrueBB, EFalseBB, ECond);
2284-
TII->removeBranch(*RegionExit);
2285-
2286-
// We need to create a backedge if there is a loop
2287-
Register Reg = TII->insertNE(
2288-
RegionExit, RegionExit->instr_end(), DL,
2289-
CurrentRegion->getRegionMRT()->getInnerOutputRegister(),
2290-
CurrentRegion->getRegionMRT()->getEntry()->getNumber());
2291-
MachineOperand RegOp =
2292-
MachineOperand::CreateReg(Reg, false, false, true);
2293-
ArrayRef<MachineOperand> Cond(RegOp);
2294-
LLVM_DEBUG(dbgs() << "RegionExitReg: ");
2295-
LLVM_DEBUG(RegOp.print(dbgs(), TRI));
2296-
LLVM_DEBUG(dbgs() << "\n");
2297-
TII->insertBranch(*RegionExit, CurrentRegion->getEntry(), RegionExit,
2298-
Cond, DebugLoc());
2299-
RegionExit->addSuccessor(CurrentRegion->getEntry());
2300-
}
2301-
}
2302-
CurrentRegion->addMBB(CodeBB);
2303-
LinearizedRegion InnerRegion(CodeBB, MRI, TRI, PHIInfo);
2260+
}
2261+
// Handle internal block.
2262+
const TargetRegisterClass *RegClass = MRI->getRegClass(BBSelectRegIn);
2263+
Register CodeBBSelectReg = MRI->createVirtualRegister(RegClass);
2264+
rewriteCodeBBTerminator(CodeBB, MergeBB, CodeBBSelectReg);
2265+
bool IsRegionEntryBB = CurrentRegion->getEntry() == CodeBB;
2266+
MachineBasicBlock *IfBB = createIfBlock(MergeBB, CodeBB, CodeBB, CodeBB,
2267+
BBSelectRegIn, IsRegionEntryBB);
2268+
CurrentRegion->addMBB(IfBB);
2269+
// If this is the entry block we need to make the If block the new
2270+
// linearized region entry.
2271+
if (IsRegionEntryBB) {
2272+
CurrentRegion->setEntry(IfBB);
2273+
2274+
if (CurrentRegion->getHasLoop()) {
2275+
MachineBasicBlock *RegionExit = CurrentRegion->getExit();
2276+
MachineBasicBlock *ETrueBB = nullptr;
2277+
MachineBasicBlock *EFalseBB = nullptr;
2278+
SmallVector<MachineOperand, 1> ECond;
23042279

2305-
InnerRegion.setParent(CurrentRegion);
2306-
LLVM_DEBUG(dbgs() << "Insert BB Select PHI (BB)\n");
2307-
insertMergePHI(IfBB, CodeBB, MergeBB, BBSelectRegOut, BBSelectRegIn,
2308-
CodeBBSelectReg);
2309-
InnerRegion.addMBB(MergeBB);
2280+
const DebugLoc &DL = DebugLoc();
2281+
TII->analyzeBranch(*RegionExit, ETrueBB, EFalseBB, ECond);
2282+
TII->removeBranch(*RegionExit);
23102283

2311-
LLVM_DEBUG(InnerRegion.print(dbgs(), TRI));
2312-
rewriteLiveOutRegs(IfBB, CodeBB, MergeBB, &InnerRegion, CurrentRegion);
2313-
extractKilledPHIs(CodeBB);
2314-
if (IsRegionEntryBB) {
2315-
createEntryPHIs(CurrentRegion);
2284+
// We need to create a backedge if there is a loop
2285+
Register Reg =
2286+
TII->insertNE(RegionExit, RegionExit->instr_end(), DL,
2287+
CurrentRegion->getRegionMRT()->getInnerOutputRegister(),
2288+
CurrentRegion->getRegionMRT()->getEntry()->getNumber());
2289+
MachineOperand RegOp = MachineOperand::CreateReg(Reg, false, false, true);
2290+
ArrayRef<MachineOperand> Cond(RegOp);
2291+
LLVM_DEBUG(dbgs() << "RegionExitReg: ");
2292+
LLVM_DEBUG(RegOp.print(dbgs(), TRI));
2293+
LLVM_DEBUG(dbgs() << "\n");
2294+
TII->insertBranch(*RegionExit, CurrentRegion->getEntry(), RegionExit,
2295+
Cond, DebugLoc());
2296+
RegionExit->addSuccessor(CurrentRegion->getEntry());
23162297
}
2317-
return IfBB;
23182298
}
2299+
CurrentRegion->addMBB(CodeBB);
2300+
LinearizedRegion InnerRegion(CodeBB, MRI, TRI, PHIInfo);
2301+
2302+
InnerRegion.setParent(CurrentRegion);
2303+
LLVM_DEBUG(dbgs() << "Insert BB Select PHI (BB)\n");
2304+
insertMergePHI(IfBB, CodeBB, MergeBB, BBSelectRegOut, BBSelectRegIn,
2305+
CodeBBSelectReg);
2306+
InnerRegion.addMBB(MergeBB);
2307+
2308+
LLVM_DEBUG(InnerRegion.print(dbgs(), TRI));
2309+
rewriteLiveOutRegs(IfBB, CodeBB, MergeBB, &InnerRegion, CurrentRegion);
2310+
extractKilledPHIs(CodeBB);
2311+
if (IsRegionEntryBB)
2312+
createEntryPHIs(CurrentRegion);
2313+
return IfBB;
23192314
}
23202315

23212316
MachineBasicBlock *AMDGPUMachineCFGStructurizer::createIfRegion(
@@ -2712,12 +2707,11 @@ bool AMDGPUMachineCFGStructurizer::structurizeRegion(RegionMRT *Region) {
27122707
if (false && regionIsSimpleIf(Region)) {
27132708
transformSimpleIfRegion(Region);
27142709
return true;
2715-
} else if (regionIsSequence(Region)) {
2710+
}
2711+
if (regionIsSequence(Region))
27162712
fixupRegionExits(Region);
2717-
return false;
2718-
} else {
2713+
else
27192714
structurizeComplexRegion(Region);
2720-
}
27212715
return false;
27222716
}
27232717

@@ -2784,12 +2778,11 @@ AMDGPUMachineCFGStructurizer::initializeSelectRegisters(MRT *MRT, unsigned Selec
27842778
InnerSelectOut = initializeSelectRegisters(CI, InnerSelectOut, MRI, TII);
27852779
MRT->setBBSelectRegIn(InnerSelectOut);
27862780
return InnerSelectOut;
2787-
} else {
2788-
MRT->setBBSelectRegOut(SelectOut);
2789-
unsigned NewSelectIn = createBBSelectReg(TII, MRI);
2790-
MRT->setBBSelectRegIn(NewSelectIn);
2791-
return NewSelectIn;
27922781
}
2782+
MRT->setBBSelectRegOut(SelectOut);
2783+
unsigned NewSelectIn = createBBSelectReg(TII, MRI);
2784+
MRT->setBBSelectRegIn(NewSelectIn);
2785+
return NewSelectIn;
27932786
}
27942787

27952788
static void checkRegOnlyPHIInputs(MachineFunction &MF) {

‎llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

Lines changed: 7 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1116,15 +1116,14 @@ bool AMDGPURegisterBankInfo::applyMappingLoad(
11161116
LegalizerHelper::Legalized)
11171117
return false;
11181118
return true;
1119+
}
1120+
LLT WiderTy = widen96To128(LoadTy);
1121+
auto WideLoad = B.buildLoadFromOffset(WiderTy, PtrReg, *MMO, 0);
1122+
if (WiderTy.isScalar()) {
1123+
B.buildTrunc(MI.getOperand(0), WideLoad);
11191124
} else {
1120-
LLT WiderTy = widen96To128(LoadTy);
1121-
auto WideLoad = B.buildLoadFromOffset(WiderTy, PtrReg, *MMO, 0);
1122-
if (WiderTy.isScalar())
1123-
B.buildTrunc(MI.getOperand(0), WideLoad);
1124-
else {
1125-
B.buildDeleteTrailingVectorElements(MI.getOperand(0).getReg(),
1126-
WideLoad);
1127-
}
1125+
B.buildDeleteTrailingVectorElements(MI.getOperand(0).getReg(),
1126+
WideLoad);
11281127
}
11291128
}
11301129

‎llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1038,15 +1038,14 @@ unsigned GCNSubtarget::getNSAThreshold(const MachineFunction &MF) const {
10381038
const AMDGPUSubtarget &AMDGPUSubtarget::get(const MachineFunction &MF) {
10391039
if (MF.getTarget().getTargetTriple().getArch() == Triple::amdgcn)
10401040
return static_cast<const AMDGPUSubtarget&>(MF.getSubtarget<GCNSubtarget>());
1041-
else
1042-
return static_cast<const AMDGPUSubtarget&>(MF.getSubtarget<R600Subtarget>());
1041+
return static_cast<const AMDGPUSubtarget &>(MF.getSubtarget<R600Subtarget>());
10431042
}
10441043

10451044
const AMDGPUSubtarget &AMDGPUSubtarget::get(const TargetMachine &TM, const Function &F) {
10461045
if (TM.getTargetTriple().getArch() == Triple::amdgcn)
10471046
return static_cast<const AMDGPUSubtarget&>(TM.getSubtarget<GCNSubtarget>(F));
1048-
else
1049-
return static_cast<const AMDGPUSubtarget&>(TM.getSubtarget<R600Subtarget>(F));
1047+
return static_cast<const AMDGPUSubtarget &>(
1048+
TM.getSubtarget<R600Subtarget>(F));
10501049
}
10511050

10521051
GCNUserSGPRUsageInfo::GCNUserSGPRUsageInfo(const Function &F,

‎llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

Lines changed: 24 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -99,13 +99,11 @@ class AMDGPUOperand : public MCParsedAsmOperand {
9999
int64_t getModifiersOperand() const {
100100
assert(!(hasFPModifiers() && hasIntModifiers())
101101
&& "fp and int modifiers should not be used simultaneously");
102-
if (hasFPModifiers()) {
102+
if (hasFPModifiers())
103103
return getFPModifiersOperand();
104-
} else if (hasIntModifiers()) {
104+
if (hasIntModifiers())
105105
return getIntModifiersOperand();
106-
} else {
107-
return 0;
108-
}
106+
return 0;
109107
}
110108

111109
friend raw_ostream &operator <<(raw_ostream &OS, AMDGPUOperand::Modifiers Mods);
@@ -2162,10 +2160,9 @@ template <bool IsFake16> bool AMDGPUOperand::isT16VRegWithInputMods() const {
21622160
bool AMDGPUOperand::isSDWAOperand(MVT type) const {
21632161
if (AsmParser->isVI())
21642162
return isVReg32();
2165-
else if (AsmParser->isGFX9Plus())
2163+
if (AsmParser->isGFX9Plus())
21662164
return isRegClass(AMDGPU::VS_32RegClassID) || isInlinableImm(type);
2167-
else
2168-
return false;
2165+
return false;
21692166
}
21702167

21712168
bool AMDGPUOperand::isSDWAFP16Operand() const {
@@ -3680,19 +3677,17 @@ static OperandIndices getSrcOperandIndices(unsigned Opcode,
36803677

36813678
bool AMDGPUAsmParser::usesConstantBus(const MCInst &Inst, unsigned OpIdx) {
36823679
const MCOperand &MO = Inst.getOperand(OpIdx);
3683-
if (MO.isImm()) {
3680+
if (MO.isImm())
36843681
return !isInlineConstant(Inst, OpIdx);
3685-
} else if (MO.isReg()) {
3682+
if (MO.isReg()) {
36863683
auto Reg = MO.getReg();
3687-
if (!Reg) {
3684+
if (!Reg)
36883685
return false;
3689-
}
36903686
const MCRegisterInfo *TRI = getContext().getRegisterInfo();
36913687
auto PReg = mc2PseudoReg(Reg);
36923688
return isSGPR(PReg, TRI) && PReg != SGPR_NULL;
3693-
} else {
3694-
return true;
36953689
}
3690+
return true;
36963691
}
36973692

36983693
// Based on the comment for `AMDGPUInstructionSelector::selectWritelane`:
@@ -6338,16 +6333,20 @@ StringRef AMDGPUAsmParser::parseMnemonicSuffix(StringRef Name) {
63386333
setForcedDPP(true);
63396334
setForcedEncodingSize(64);
63406335
return Name.substr(0, Name.size() - 8);
6341-
} else if (Name.ends_with("_e64")) {
6336+
}
6337+
if (Name.ends_with("_e64")) {
63426338
setForcedEncodingSize(64);
63436339
return Name.substr(0, Name.size() - 4);
6344-
} else if (Name.ends_with("_e32")) {
6340+
}
6341+
if (Name.ends_with("_e32")) {
63456342
setForcedEncodingSize(32);
63466343
return Name.substr(0, Name.size() - 4);
6347-
} else if (Name.ends_with("_dpp")) {
6344+
}
6345+
if (Name.ends_with("_dpp")) {
63486346
setForcedDPP(true);
63496347
return Name.substr(0, Name.size() - 4);
6350-
} else if (Name.ends_with("_sdwa")) {
6348+
}
6349+
if (Name.ends_with("_sdwa")) {
63516350
setForcedSDWA(true);
63526351
return Name.substr(0, Name.size() - 5);
63536352
}
@@ -7754,10 +7753,9 @@ AMDGPUAsmParser::parseString(StringRef &Val, const StringRef ErrMsg) {
77547753
Val = getToken().getStringContents();
77557754
lex();
77567755
return true;
7757-
} else {
7758-
Error(getLoc(), ErrMsg);
7759-
return false;
77607756
}
7757+
Error(getLoc(), ErrMsg);
7758+
return false;
77617759
}
77627760

77637761
bool
@@ -7766,11 +7764,10 @@ AMDGPUAsmParser::parseId(StringRef &Val, const StringRef ErrMsg) {
77667764
Val = getTokenStr();
77677765
lex();
77687766
return true;
7769-
} else {
7770-
if (!ErrMsg.empty())
7771-
Error(getLoc(), ErrMsg);
7772-
return false;
77737767
}
7768+
if (!ErrMsg.empty())
7769+
Error(getLoc(), ErrMsg);
7770+
return false;
77747771
}
77757772

77767773
AsmToken
@@ -9475,8 +9472,8 @@ void AMDGPUAsmParser::cvtSDWA(MCInst &Inst, const OperandVector &Operands,
94759472
(SkipSrcVcc && Inst.getNumOperands() == 5))) {
94769473
SkippedVcc = true;
94779474
continue;
9478-
} else if (BasicInstType == SIInstrFlags::VOPC &&
9479-
Inst.getNumOperands() == 0) {
9475+
}
9476+
if (BasicInstType == SIInstrFlags::VOPC && Inst.getNumOperands() == 0) {
94809477
SkippedVcc = true;
94819478
continue;
94829479
}

‎llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp

Lines changed: 10 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1566,8 +1566,7 @@ AMDGPUDisassembler::decodeNonVGPRSrcOp(const OpWidthTy Width, unsigned Val,
15661566
if (MandatoryLiteral)
15671567
// Keep a sentinel value for deferred setting
15681568
return MCOperand::createImm(LITERAL_CONST);
1569-
else
1570-
return decodeLiteralConstant(Sema == AMDGPU::OperandSemantics::FP64);
1569+
return decodeLiteralConstant(Sema == AMDGPU::OperandSemantics::FP64);
15711570
}
15721571

15731572
switch (Width) {
@@ -1701,9 +1700,9 @@ AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width, const unsigned Val,
17011700
return decodeFPImmed(ImmWidth, SVal, Sema);
17021701

17031702
return decodeSpecialReg32(SVal);
1704-
} else if (STI.hasFeature(AMDGPU::FeatureVolcanicIslands)) {
1705-
return createRegOperand(getVgprClassId(Width), Val);
17061703
}
1704+
if (STI.hasFeature(AMDGPU::FeatureVolcanicIslands))
1705+
return createRegOperand(getVgprClassId(Width), Val);
17071706
llvm_unreachable("unsupported target");
17081707
}
17091708

@@ -1731,15 +1730,13 @@ MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const {
17311730
if (TTmpIdx >= 0) {
17321731
auto TTmpClsId = getTtmpClassId(IsWave64 ? OPW64 : OPW32);
17331732
return createSRegOperand(TTmpClsId, TTmpIdx);
1734-
} else if (Val > SGPR_MAX) {
1735-
return IsWave64 ? decodeSpecialReg64(Val)
1736-
: decodeSpecialReg32(Val);
1737-
} else {
1738-
return createSRegOperand(getSgprClassId(IsWave64 ? OPW64 : OPW32), Val);
17391733
}
1740-
} else {
1741-
return createRegOperand(IsWave64 ? AMDGPU::VCC : AMDGPU::VCC_LO);
1734+
if (Val > SGPR_MAX) {
1735+
return IsWave64 ? decodeSpecialReg64(Val) : decodeSpecialReg32(Val);
1736+
}
1737+
return createSRegOperand(getSgprClassId(IsWave64 ? OPW64 : OPW32), Val);
17421738
}
1739+
return createRegOperand(IsWave64 ? AMDGPU::VCC : AMDGPU::VCC_LO);
17431740
}
17441741

17451742
MCOperand AMDGPUDisassembler::decodeBoolReg(unsigned Val) const {
@@ -2265,7 +2262,8 @@ Expected<bool> AMDGPUDisassembler::decodeKernelDescriptorDirective(
22652262
return createReservedKDBitsError(
22662263
KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32,
22672264
amdhsa::KERNEL_CODE_PROPERTIES_OFFSET, "must be zero on gfx9");
2268-
} else if (isGFX10Plus()) {
2265+
}
2266+
if (isGFX10Plus()) {
22692267
PRINT_DIRECTIVE(".amdhsa_wavefront_size32",
22702268
KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32);
22712269
}

0 commit comments

Comments
 (0)