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VyacheslavLevytskyyVyacheslavLevytskyy
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[SPIR-V] Rework usage of virtual registers' types and classes (#104104)
This PR continues #101732 changes in virtual register processing aimed to improve correctness of emitted MIR between passes from the perspective of MachineVerifier. Namely, the following changes are introduced: * register classes (lib/Target/SPIRV/SPIRVRegisterInfo.td) and instruction patterns (lib/Target/SPIRV/SPIRVInstrInfo.td) are corrected and simplified (by removing unnecessary sophisticated options) -- e.g., this PR gets rid of duplicating 32/64 bits patterns, removes ANYID register class and simplifies definition of the rest of register classes, * hardcoded LLT scalar types in passes before instruction selection are corrected -- the goal is to have correct bit width before instruction selection, and use 64 bits registers for pattern matching in the instruction selection pass; 32-bit registers remain where they are described in such terms by SPIR-V specification (like, for example, creation of virtual registers for scope/mem semantics operands), * rework virtual register type/class assignment for calls/builtins lowering, * a series of minor changes to fix validity of emitted code between passes: - ensure that that bitcast changes the type, - fix the pattern for instruction selection for OpExtInst, - simplify inline asm operands usage, - account for arbitrary integer sizes / update legalizer rules; * add '-verify-machineinstrs' to existed test cases. See also #88129 that this PR may resolve. This PR fixes a great number of issues reported by MachineVerifier and, as a result, reduces a number of failed test cases for the mode with expensive checks set on from ~200 to ~57.
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‎llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCCodeEmitter.cpp

+2-1
Original file line numberDiff line numberDiff line change
@@ -67,7 +67,8 @@ static bool hasType(const MCInst &MI, const MCInstrInfo &MII) {
6767
// Check if we define an ID, and take a type as operand 1.
6868
auto &DefOpInfo = MCDesc.operands()[0];
6969
auto &FirstArgOpInfo = MCDesc.operands()[1];
70-
return DefOpInfo.RegClass != SPIRV::TYPERegClassID &&
70+
return DefOpInfo.RegClass >= 0 && FirstArgOpInfo.RegClass >= 0 &&
71+
DefOpInfo.RegClass != SPIRV::TYPERegClassID &&
7172
FirstArgOpInfo.RegClass == SPIRV::TYPERegClassID;
7273
}
7374
return false;

‎llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp

+82-172
Large diffs are not rendered by default.

‎llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp

+18-9
Original file line numberDiff line numberDiff line change
@@ -371,7 +371,7 @@ bool SPIRVCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
371371
}
372372

373373
auto MRI = MIRBuilder.getMRI();
374-
Register FuncVReg = MRI->createGenericVirtualRegister(LLT::scalar(32));
374+
Register FuncVReg = MRI->createGenericVirtualRegister(LLT::scalar(64));
375375
MRI->setRegClass(FuncVReg, &SPIRV::iIDRegClass);
376376
if (F.isDeclaration())
377377
GR->add(&F, &MIRBuilder.getMF(), FuncVReg);
@@ -403,12 +403,14 @@ bool SPIRVCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
403403
int i = 0;
404404
for (const auto &Arg : F.args()) {
405405
assert(VRegs[i].size() == 1 && "Formal arg has multiple vregs");
406-
MRI->setRegClass(VRegs[i][0], &SPIRV::iIDRegClass);
406+
Register ArgReg = VRegs[i][0];
407+
MRI->setRegClass(ArgReg, GR->getRegClass(ArgTypeVRegs[i]));
408+
MRI->setType(ArgReg, GR->getRegType(ArgTypeVRegs[i]));
407409
MIRBuilder.buildInstr(SPIRV::OpFunctionParameter)
408-
.addDef(VRegs[i][0])
410+
.addDef(ArgReg)
409411
.addUse(GR->getSPIRVTypeID(ArgTypeVRegs[i]));
410412
if (F.isDeclaration())
411-
GR->add(&Arg, &MIRBuilder.getMF(), VRegs[i][0]);
413+
GR->add(&Arg, &MIRBuilder.getMF(), ArgReg);
412414
i++;
413415
}
414416
// Name the function.
@@ -532,10 +534,17 @@ bool SPIRVCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
532534
SmallVector<Register, 8> ArgVRegs;
533535
for (auto Arg : Info.OrigArgs) {
534536
assert(Arg.Regs.size() == 1 && "Call arg has multiple VRegs");
535-
ArgVRegs.push_back(Arg.Regs[0]);
536-
SPIRVType *SPIRVTy = GR->getOrCreateSPIRVType(Arg.Ty, MIRBuilder);
537-
if (!GR->getSPIRVTypeForVReg(Arg.Regs[0]))
538-
GR->assignSPIRVTypeToVReg(SPIRVTy, Arg.Regs[0], MF);
537+
Register ArgReg = Arg.Regs[0];
538+
ArgVRegs.push_back(ArgReg);
539+
SPIRVType *SpvType = GR->getSPIRVTypeForVReg(ArgReg);
540+
if (!SpvType) {
541+
SpvType = GR->getOrCreateSPIRVType(Arg.Ty, MIRBuilder);
542+
GR->assignSPIRVTypeToVReg(SpvType, ArgReg, MF);
543+
}
544+
if (!MRI->getRegClassOrNull(ArgReg)) {
545+
MRI->setRegClass(ArgReg, GR->getRegClass(SpvType));
546+
MRI->setType(ArgReg, GR->getRegType(SpvType));
547+
}
539548
}
540549
auto instructionSet = canUseOpenCL ? SPIRV::InstructionSet::OpenCL_std
541550
: SPIRV::InstructionSet::GLSL_std_450;
@@ -557,7 +566,7 @@ bool SPIRVCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
557566
for (const Argument &Arg : CF->args()) {
558567
if (MIRBuilder.getDataLayout().getTypeStoreSize(Arg.getType()).isZero())
559568
continue; // Don't handle zero sized types.
560-
Register Reg = MRI->createGenericVirtualRegister(LLT::scalar(32));
569+
Register Reg = MRI->createGenericVirtualRegister(LLT::scalar(64));
561570
MRI->setRegClass(Reg, &SPIRV::iIDRegClass);
562571
ToInsert.push_back({Reg});
563572
VRegArgs.push_back(ToInsert.back());

‎llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp

+100-55
Original file line numberDiff line numberDiff line change
@@ -72,17 +72,14 @@ void SPIRVGlobalRegistry::assignSPIRVTypeToVReg(SPIRVType *SpirvType,
7272
VRegToTypeMap[&MF][VReg] = SpirvType;
7373
}
7474

75-
static Register createTypeVReg(MachineIRBuilder &MIRBuilder) {
76-
auto &MRI = MIRBuilder.getMF().getRegInfo();
77-
auto Res = MRI.createGenericVirtualRegister(LLT::scalar(32));
75+
static Register createTypeVReg(MachineRegisterInfo &MRI) {
76+
auto Res = MRI.createGenericVirtualRegister(LLT::scalar(64));
7877
MRI.setRegClass(Res, &SPIRV::TYPERegClass);
7978
return Res;
8079
}
8180

82-
static Register createTypeVReg(MachineRegisterInfo &MRI) {
83-
auto Res = MRI.createGenericVirtualRegister(LLT::scalar(32));
84-
MRI.setRegClass(Res, &SPIRV::TYPERegClass);
85-
return Res;
81+
inline Register createTypeVReg(MachineIRBuilder &MIRBuilder) {
82+
return createTypeVReg(MIRBuilder.getMF().getRegInfo());
8683
}
8784

8885
SPIRVType *SPIRVGlobalRegistry::getOpTypeBool(MachineIRBuilder &MIRBuilder) {
@@ -157,26 +154,24 @@ SPIRVType *SPIRVGlobalRegistry::getOpTypeVector(uint32_t NumElems,
157154
return MIB;
158155
}
159156

160-
std::tuple<Register, ConstantInt *, bool>
157+
std::tuple<Register, ConstantInt *, bool, unsigned>
161158
SPIRVGlobalRegistry::getOrCreateConstIntReg(uint64_t Val, SPIRVType *SpvType,
162159
MachineIRBuilder *MIRBuilder,
163160
MachineInstr *I,
164161
const SPIRVInstrInfo *TII) {
165-
const IntegerType *LLVMIntTy;
166-
if (SpvType)
167-
LLVMIntTy = cast<IntegerType>(getTypeForSPIRVType(SpvType));
168-
else
169-
LLVMIntTy = IntegerType::getInt32Ty(CurMF->getFunction().getContext());
162+
assert(SpvType);
163+
const IntegerType *LLVMIntTy =
164+
cast<IntegerType>(getTypeForSPIRVType(SpvType));
165+
unsigned BitWidth = getScalarOrVectorBitWidth(SpvType);
170166
bool NewInstr = false;
171167
// Find a constant in DT or build a new one.
172168
ConstantInt *CI = ConstantInt::get(const_cast<IntegerType *>(LLVMIntTy), Val);
173169
Register Res = DT.find(CI, CurMF);
174170
if (!Res.isValid()) {
175-
unsigned BitWidth = SpvType ? getScalarOrVectorBitWidth(SpvType) : 32;
176171
// TODO: handle cases where the type is not 32bit wide
177172
// TODO: https://github.com/llvm/llvm-project/issues/88129
178-
LLT LLTy = LLT::scalar(32);
179-
Res = CurMF->getRegInfo().createGenericVirtualRegister(LLTy);
173+
Res =
174+
CurMF->getRegInfo().createGenericVirtualRegister(LLT::scalar(BitWidth));
180175
CurMF->getRegInfo().setRegClass(Res, &SPIRV::iIDRegClass);
181176
if (MIRBuilder)
182177
assignTypeToVReg(LLVMIntTy, Res, *MIRBuilder);
@@ -185,35 +180,27 @@ SPIRVGlobalRegistry::getOrCreateConstIntReg(uint64_t Val, SPIRVType *SpvType,
185180
DT.add(CI, CurMF, Res);
186181
NewInstr = true;
187182
}
188-
return std::make_tuple(Res, CI, NewInstr);
183+
return std::make_tuple(Res, CI, NewInstr, BitWidth);
189184
}
190185

191186
std::tuple<Register, ConstantFP *, bool, unsigned>
192187
SPIRVGlobalRegistry::getOrCreateConstFloatReg(APFloat Val, SPIRVType *SpvType,
193188
MachineIRBuilder *MIRBuilder,
194189
MachineInstr *I,
195190
const SPIRVInstrInfo *TII) {
196-
const Type *LLVMFloatTy;
191+
assert(SpvType);
197192
LLVMContext &Ctx = CurMF->getFunction().getContext();
198-
unsigned BitWidth = 32;
199-
if (SpvType)
200-
LLVMFloatTy = getTypeForSPIRVType(SpvType);
201-
else {
202-
LLVMFloatTy = Type::getFloatTy(Ctx);
203-
if (MIRBuilder)
204-
SpvType = getOrCreateSPIRVType(LLVMFloatTy, *MIRBuilder);
205-
}
193+
const Type *LLVMFloatTy = getTypeForSPIRVType(SpvType);
194+
unsigned BitWidth = getScalarOrVectorBitWidth(SpvType);
206195
bool NewInstr = false;
207196
// Find a constant in DT or build a new one.
208197
auto *const CI = ConstantFP::get(Ctx, Val);
209198
Register Res = DT.find(CI, CurMF);
210199
if (!Res.isValid()) {
211-
if (SpvType)
212-
BitWidth = getScalarOrVectorBitWidth(SpvType);
213200
// TODO: handle cases where the type is not 32bit wide
214201
// TODO: https://github.com/llvm/llvm-project/issues/88129
215-
LLT LLTy = LLT::scalar(32);
216-
Res = CurMF->getRegInfo().createGenericVirtualRegister(LLTy);
202+
Res =
203+
CurMF->getRegInfo().createGenericVirtualRegister(LLT::scalar(BitWidth));
217204
CurMF->getRegInfo().setRegClass(Res, &SPIRV::fIDRegClass);
218205
if (MIRBuilder)
219206
assignTypeToVReg(LLVMFloatTy, Res, *MIRBuilder);
@@ -269,7 +256,8 @@ Register SPIRVGlobalRegistry::getOrCreateConstInt(uint64_t Val, MachineInstr &I,
269256
ConstantInt *CI;
270257
Register Res;
271258
bool New;
272-
std::tie(Res, CI, New) =
259+
unsigned BitWidth;
260+
std::tie(Res, CI, New, BitWidth) =
273261
getOrCreateConstIntReg(Val, SpvType, nullptr, &I, &TII);
274262
// If we have found Res register which is defined by the passed G_CONSTANT
275263
// machine instruction, a new constant instruction should be created.
@@ -281,7 +269,7 @@ Register SPIRVGlobalRegistry::getOrCreateConstInt(uint64_t Val, MachineInstr &I,
281269
MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpConstantI))
282270
.addDef(Res)
283271
.addUse(getSPIRVTypeID(SpvType));
284-
addNumImm(APInt(getScalarOrVectorBitWidth(SpvType), Val), MIB);
272+
addNumImm(APInt(BitWidth, Val), MIB);
285273
} else {
286274
MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpConstantNull))
287275
.addDef(Res)
@@ -297,19 +285,17 @@ Register SPIRVGlobalRegistry::buildConstantInt(uint64_t Val,
297285
MachineIRBuilder &MIRBuilder,
298286
SPIRVType *SpvType,
299287
bool EmitIR) {
288+
assert(SpvType);
300289
auto &MF = MIRBuilder.getMF();
301-
const IntegerType *LLVMIntTy;
302-
if (SpvType)
303-
LLVMIntTy = cast<IntegerType>(getTypeForSPIRVType(SpvType));
304-
else
305-
LLVMIntTy = IntegerType::getInt32Ty(MF.getFunction().getContext());
290+
const IntegerType *LLVMIntTy =
291+
cast<IntegerType>(getTypeForSPIRVType(SpvType));
306292
// Find a constant in DT or build a new one.
307293
const auto ConstInt =
308294
ConstantInt::get(const_cast<IntegerType *>(LLVMIntTy), Val);
309295
Register Res = DT.find(ConstInt, &MF);
310296
if (!Res.isValid()) {
311-
unsigned BitWidth = SpvType ? getScalarOrVectorBitWidth(SpvType) : 32;
312-
LLT LLTy = LLT::scalar(EmitIR ? BitWidth : 32);
297+
unsigned BitWidth = getScalarOrVectorBitWidth(SpvType);
298+
LLT LLTy = LLT::scalar(BitWidth);
313299
Res = MF.getRegInfo().createGenericVirtualRegister(LLTy);
314300
MF.getRegInfo().setRegClass(Res, &SPIRV::iIDRegClass);
315301
assignTypeToVReg(LLVMIntTy, Res, MIRBuilder,
@@ -318,18 +304,17 @@ Register SPIRVGlobalRegistry::buildConstantInt(uint64_t Val,
318304
if (EmitIR) {
319305
MIRBuilder.buildConstant(Res, *ConstInt);
320306
} else {
321-
if (!SpvType)
322-
SpvType = getOrCreateSPIRVIntegerType(BitWidth, MIRBuilder);
307+
Register SpvTypeReg = getSPIRVTypeID(SpvType);
323308
MachineInstrBuilder MIB;
324309
if (Val) {
325310
MIB = MIRBuilder.buildInstr(SPIRV::OpConstantI)
326311
.addDef(Res)
327-
.addUse(getSPIRVTypeID(SpvType));
312+
.addUse(SpvTypeReg);
328313
addNumImm(APInt(BitWidth, Val), MIB);
329314
} else {
330315
MIB = MIRBuilder.buildInstr(SPIRV::OpConstantNull)
331316
.addDef(Res)
332-
.addUse(getSPIRVTypeID(SpvType));
317+
.addUse(SpvTypeReg);
333318
}
334319
const auto &Subtarget = CurMF->getSubtarget();
335320
constrainSelectedInstRegOperands(*MIB, *Subtarget.getInstrInfo(),
@@ -353,7 +338,8 @@ Register SPIRVGlobalRegistry::buildConstantFP(APFloat Val,
353338
const auto ConstFP = ConstantFP::get(Ctx, Val);
354339
Register Res = DT.find(ConstFP, &MF);
355340
if (!Res.isValid()) {
356-
Res = MF.getRegInfo().createGenericVirtualRegister(LLT::scalar(32));
341+
Res = MF.getRegInfo().createGenericVirtualRegister(
342+
LLT::scalar(getScalarOrVectorBitWidth(SpvType)));
357343
MF.getRegInfo().setRegClass(Res, &SPIRV::fIDRegClass);
358344
assignSPIRVTypeToVReg(SpvType, Res, MF);
359345
DT.add(ConstFP, &MF, Res);
@@ -407,7 +393,7 @@ Register SPIRVGlobalRegistry::getOrCreateCompositeOrNull(
407393

408394
// TODO: handle cases where the type is not 32bit wide
409395
// TODO: https://github.com/llvm/llvm-project/issues/88129
410-
LLT LLTy = LLT::scalar(32);
396+
LLT LLTy = LLT::scalar(64);
411397
Register SpvVecConst =
412398
CurMF->getRegInfo().createGenericVirtualRegister(LLTy);
413399
CurMF->getRegInfo().setRegClass(SpvVecConst, &SPIRV::iIDRegClass);
@@ -509,7 +495,7 @@ Register SPIRVGlobalRegistry::getOrCreateIntCompositeOrNull(
509495
getOrCreateSPIRVIntegerType(BitWidth, MIRBuilder);
510496
SpvScalConst = buildConstantInt(Val, MIRBuilder, SpvBaseType, EmitIR);
511497
}
512-
LLT LLTy = EmitIR ? LLT::fixed_vector(ElemCnt, BitWidth) : LLT::scalar(32);
498+
LLT LLTy = EmitIR ? LLT::fixed_vector(ElemCnt, BitWidth) : LLT::scalar(64);
513499
Register SpvVecConst =
514500
CurMF->getRegInfo().createGenericVirtualRegister(LLTy);
515501
CurMF->getRegInfo().setRegClass(SpvVecConst, &SPIRV::iIDRegClass);
@@ -650,7 +636,6 @@ Register SPIRVGlobalRegistry::buildGlobalVariable(
650636

651637
// Set to Reg the same type as ResVReg has.
652638
auto MRI = MIRBuilder.getMRI();
653-
assert(MRI->getType(ResVReg).isPointer() && "Pointer type is expected");
654639
if (Reg != ResVReg) {
655640
LLT RegLLTy =
656641
LLT::pointer(MRI->getType(ResVReg).getAddressSpace(), getPointerSize());
@@ -706,8 +691,9 @@ SPIRVType *SPIRVGlobalRegistry::getOpTypeArray(uint32_t NumElems,
706691
bool EmitIR) {
707692
assert((ElemType->getOpcode() != SPIRV::OpTypeVoid) &&
708693
"Invalid array element type");
694+
SPIRVType *SpvTypeInt32 = getOrCreateSPIRVIntegerType(32, MIRBuilder);
709695
Register NumElementsVReg =
710-
buildConstantInt(NumElems, MIRBuilder, nullptr, EmitIR);
696+
buildConstantInt(NumElems, MIRBuilder, SpvTypeInt32, EmitIR);
711697
auto MIB = MIRBuilder.buildInstr(SPIRV::OpTypeArray)
712698
.addDef(createTypeVReg(MIRBuilder))
713699
.addUse(getSPIRVTypeID(ElemType))
@@ -1188,14 +1174,15 @@ SPIRVType *SPIRVGlobalRegistry::getOrCreateOpTypeCoopMatr(
11881174
if (ResVReg.isValid())
11891175
return MIRBuilder.getMF().getRegInfo().getUniqueVRegDef(ResVReg);
11901176
ResVReg = createTypeVReg(MIRBuilder);
1177+
SPIRVType *SpvTypeInt32 = getOrCreateSPIRVIntegerType(32, MIRBuilder);
11911178
SPIRVType *SpirvTy =
11921179
MIRBuilder.buildInstr(SPIRV::OpTypeCooperativeMatrixKHR)
11931180
.addDef(ResVReg)
11941181
.addUse(getSPIRVTypeID(ElemType))
1195-
.addUse(buildConstantInt(Scope, MIRBuilder, nullptr, true))
1196-
.addUse(buildConstantInt(Rows, MIRBuilder, nullptr, true))
1197-
.addUse(buildConstantInt(Columns, MIRBuilder, nullptr, true))
1198-
.addUse(buildConstantInt(Use, MIRBuilder, nullptr, true));
1182+
.addUse(buildConstantInt(Scope, MIRBuilder, SpvTypeInt32, true))
1183+
.addUse(buildConstantInt(Rows, MIRBuilder, SpvTypeInt32, true))
1184+
.addUse(buildConstantInt(Columns, MIRBuilder, SpvTypeInt32, true))
1185+
.addUse(buildConstantInt(Use, MIRBuilder, SpvTypeInt32, true));
11991186
DT.add(ExtensionType, &MIRBuilder.getMF(), ResVReg);
12001187
return SpirvTy;
12011188
}
@@ -1386,8 +1373,8 @@ SPIRVType *SPIRVGlobalRegistry::getOrCreateSPIRVArrayType(
13861373
if (Reg.isValid())
13871374
return getSPIRVTypeForVReg(Reg);
13881375
MachineBasicBlock &BB = *I.getParent();
1389-
SPIRVType *SpirvType = getOrCreateSPIRVIntegerType(32, I, TII);
1390-
Register Len = getOrCreateConstInt(NumElements, I, SpirvType, TII);
1376+
SPIRVType *SpvTypeInt32 = getOrCreateSPIRVIntegerType(32, I, TII);
1377+
Register Len = getOrCreateConstInt(NumElements, I, SpvTypeInt32, TII);
13911378
auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpTypeArray))
13921379
.addDef(createTypeVReg(CurMF->getRegInfo()))
13931380
.addUse(getSPIRVTypeID(BaseType))
@@ -1436,7 +1423,7 @@ Register SPIRVGlobalRegistry::getOrCreateUndef(MachineInstr &I,
14361423
Register Res = DT.find(UV, CurMF);
14371424
if (Res.isValid())
14381425
return Res;
1439-
LLT LLTy = LLT::scalar(32);
1426+
LLT LLTy = LLT::scalar(64);
14401427
Res = CurMF->getRegInfo().createGenericVirtualRegister(LLTy);
14411428
CurMF->getRegInfo().setRegClass(Res, &SPIRV::iIDRegClass);
14421429
assignSPIRVTypeToVReg(SpvType, Res, *CurMF);
@@ -1451,3 +1438,61 @@ Register SPIRVGlobalRegistry::getOrCreateUndef(MachineInstr &I,
14511438
*ST.getRegisterInfo(), *ST.getRegBankInfo());
14521439
return Res;
14531440
}
1441+
1442+
const TargetRegisterClass *
1443+
SPIRVGlobalRegistry::getRegClass(SPIRVType *SpvType) const {
1444+
unsigned Opcode = SpvType->getOpcode();
1445+
switch (Opcode) {
1446+
case SPIRV::OpTypeFloat:
1447+
return &SPIRV::fIDRegClass;
1448+
case SPIRV::OpTypePointer:
1449+
return &SPIRV::pIDRegClass;
1450+
case SPIRV::OpTypeVector: {
1451+
SPIRVType *ElemType = getSPIRVTypeForVReg(SpvType->getOperand(1).getReg());
1452+
unsigned ElemOpcode = ElemType ? ElemType->getOpcode() : 0;
1453+
if (ElemOpcode == SPIRV::OpTypeFloat)
1454+
return &SPIRV::vfIDRegClass;
1455+
if (ElemOpcode == SPIRV::OpTypePointer)
1456+
return &SPIRV::vpIDRegClass;
1457+
return &SPIRV::vIDRegClass;
1458+
}
1459+
}
1460+
return &SPIRV::iIDRegClass;
1461+
}
1462+
1463+
inline unsigned getAS(SPIRVType *SpvType) {
1464+
return storageClassToAddressSpace(
1465+
static_cast<SPIRV::StorageClass::StorageClass>(
1466+
SpvType->getOperand(1).getImm()));
1467+
}
1468+
1469+
LLT SPIRVGlobalRegistry::getRegType(SPIRVType *SpvType) const {
1470+
unsigned Opcode = SpvType ? SpvType->getOpcode() : 0;
1471+
switch (Opcode) {
1472+
case SPIRV::OpTypeInt:
1473+
case SPIRV::OpTypeFloat:
1474+
case SPIRV::OpTypeBool:
1475+
return LLT::scalar(getScalarOrVectorBitWidth(SpvType));
1476+
case SPIRV::OpTypePointer:
1477+
return LLT::pointer(getAS(SpvType), getPointerSize());
1478+
case SPIRV::OpTypeVector: {
1479+
SPIRVType *ElemType = getSPIRVTypeForVReg(SpvType->getOperand(1).getReg());
1480+
LLT ET;
1481+
switch (ElemType ? ElemType->getOpcode() : 0) {
1482+
case SPIRV::OpTypePointer:
1483+
ET = LLT::pointer(getAS(ElemType), getPointerSize());
1484+
break;
1485+
case SPIRV::OpTypeInt:
1486+
case SPIRV::OpTypeFloat:
1487+
case SPIRV::OpTypeBool:
1488+
ET = LLT::scalar(getScalarOrVectorBitWidth(ElemType));
1489+
break;
1490+
default:
1491+
ET = LLT::scalar(64);
1492+
}
1493+
return LLT::fixed_vector(
1494+
static_cast<unsigned>(SpvType->getOperand(2).getImm()), ET);
1495+
}
1496+
}
1497+
return LLT::scalar(64);
1498+
}

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