different true16/fake16 patterns

Author: arsenm

llvm/lib/Target/AMDGPU/SIInstructions.td

@@ -2163,23 +2163,44 @@ def : GCNPat <
   (S_MOV_B32 $ga)
 >;
 
-def : GCNPat <
-  (VGPRImm<(i16 imm)>:$imm),
-  (V_MOV_B32_e32 imm:$imm)
->;
+foreach pred = [NotHasTrue16BitInsts, UseFakeTrue16Insts] in {
+  let True16Predicate = pred in {
+    def : GCNPat <
+      (VGPRImm<(i16 imm)>:$imm),
+      (V_MOV_B32_e32 imm:$imm)
+    >;
+  }
 
-// FIXME: Workaround for ordering issue with peephole optimizer where
-// a register class copy interferes with immediate folding.  Should
-// use s_mov_b32, which can be shrunk to s_movk_i32
-def : GCNPat <
-  (VGPRImm<(f16 fpimm)>:$imm),
-  (V_MOV_B32_e32 (f16 (bitcast_fpimm_to_i32 $imm)))
->;
+  // FIXME: Workaround for ordering issue with peephole optimizer where
+  // a register class copy interferes with immediate folding.  Should
+  // use s_mov_b32, which can be shrunk to s_movk_i32
+  def : GCNPat <
+    (VGPRImm<(f16 fpimm)>:$imm),
+    (V_MOV_B32_e32 (f16 (bitcast_fpimm_to_i32 $imm)))
+  >;
 
-def : GCNPat <
-  (VGPRImm<(bf16 fpimm)>:$imm),
-  (V_MOV_B32_e32 (bf16 (bitcast_fpimm_to_i32 $imm)))
->;
+  def : GCNPat <
+    (VGPRImm<(bf16 fpimm)>:$imm),
+    (V_MOV_B32_e32 (bf16 (bitcast_fpimm_to_i32 $imm)))
+  >;
+}
+
+let True16Predicate = UseRealTrue16Insts in {
+  def : GCNPat <
+    (VGPRImm<(i16 imm)>:$imm),
+    (V_MOV_B16_t16_e64 0, imm:$imm, 0)
+  >;
+
+  def : GCNPat <
+    (VGPRImm<(f16 fpimm)>:$imm),
+    (V_MOV_B16_t16_e64 0, $imm, 0)
+  >;
+
+  def : GCNPat <
+    (VGPRImm<(bf16 fpimm)>:$imm),
+    (V_MOV_B16_t16_e64 0, $imm, 0)
+  >;
+}
 
 // V_MOV_B64_PSEUDO and S_MOV_B64_IMM_PSEUDO can be used with any 64-bit
 // immediate and wil be expanded as needed, but we will only use these patterns