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- // RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -emit-llvm < %s | FileCheck %s \
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- // RUN: --check-prefix=CHECK-X86
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- // RUN: %clang_cc1 -triple ppc64le-linux-gnu -emit-llvm < %s | FileCheck %s \
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+ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 3
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+ // RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -emit-llvm -o - %s | \
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+ // RUN: FileCheck %s --check-prefix=CHECK-X86
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+ // RUN: %clang_cc1 -triple ppc64le-linux-gnu -emit-llvm -o - %s | FileCheck %s \
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// RUN: --check-prefix=CHECK-PPC
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#ifndef __PPC__
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// global, the bit grab, and the icmp correct.
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extern void a (const char * );
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- // CHECK-X86: @__cpu_model = external dso_local global { i32, i32, i32, [1 x i32] }
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- // CHECK-X86: @__cpu_features2 = external dso_local global [3 x i32]
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+ // CHECK-X86-LABEL: define dso_local i32 @main(
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+ // CHECK-X86-SAME: ) #[[ATTR0:[0-9]+]] {
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+ // CHECK-X86-NEXT: entry:
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+ // CHECK-X86-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
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+ // CHECK-X86-NEXT: store i32 0, ptr [[RETVAL]], align 4
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+ // CHECK-X86-NEXT: call void @__cpu_indicator_init()
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+ // CHECK-X86-NEXT: [[TMP0:%.*]] = load i32, ptr getelementptr inbounds ({ i32, i32, i32, [1 x i32] }, ptr @__cpu_model, i32 0, i32 3, i32 0), align 4
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+ // CHECK-X86-NEXT: [[TMP1:%.*]] = and i32 [[TMP0]], 256
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+ // CHECK-X86-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 256
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+ // CHECK-X86-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
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+ // CHECK-X86-NEXT: br i1 [[TMP3]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
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+ // CHECK-X86: if.then:
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+ // CHECK-X86-NEXT: call void @a(ptr noundef @.str)
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+ // CHECK-X86-NEXT: br label [[IF_END]]
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+ // CHECK-X86: if.end:
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+ // CHECK-X86-NEXT: [[TMP4:%.*]] = load i32, ptr @__cpu_features2, align 4
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+ // CHECK-X86-NEXT: [[TMP5:%.*]] = and i32 [[TMP4]], 1
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+ // CHECK-X86-NEXT: [[TMP6:%.*]] = icmp eq i32 [[TMP5]], 1
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+ // CHECK-X86-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]]
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+ // CHECK-X86-NEXT: br i1 [[TMP7]], label [[IF_THEN1:%.*]], label [[IF_END2:%.*]]
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+ // CHECK-X86: if.then1:
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+ // CHECK-X86-NEXT: call void @a(ptr noundef @.str.1)
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+ // CHECK-X86-NEXT: br label [[IF_END2]]
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+ // CHECK-X86: if.end2:
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+ // CHECK-X86-NEXT: ret i32 0
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+ //
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int main (void ) {
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__builtin_cpu_init ();
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@@ -20,51 +45,111 @@ int main(void) {
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if (__builtin_cpu_supports ("sse4.2" ))
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a ("sse4.2" );
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- // CHECK-X86: [[LOAD:%[^ ]+]] = load i32, ptr getelementptr inbounds ({ i32, i32, i32, [1 x i32] }, ptr @__cpu_model, i32 0, i32 3, i32 0)
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- // CHECK-X86: [[AND:%[^ ]+]] = and i32 [[LOAD]], 256
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- // CHECK-X86: = icmp eq i32 [[AND]], 256
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if (__builtin_cpu_supports ("gfni" ))
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a ("gfni" );
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- // CHECK-X86: [[LOAD:%[^ ]+]] = load i32, ptr @__cpu_features2
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- // CHECK-X86: [[AND:%[^ ]+]] = and i32 [[LOAD]], 1
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- // CHECK-X86: = icmp eq i32 [[AND]], 1
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return 0 ;
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}
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- // CHECK-X86: declare dso_local void @__cpu_indicator_init()
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- // CHECK-X86-LABEL: define{{.*}} @baseline(
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- // CHECK-X86: [[LOAD:%.*]] = load i32, ptr getelementptr inbounds ([[[#]] x i32], ptr @__cpu_features2, i32 0, i32 1)
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- // CHECK-X86-NEXT: and i32 [[LOAD]], -2147483648
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+ // CHECK-X86-LABEL: define dso_local i32 @baseline(
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+ // CHECK-X86-SAME: ) #[[ATTR0]] {
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+ // CHECK-X86-NEXT: entry:
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+ // CHECK-X86-NEXT: [[TMP0:%.*]] = load i32, ptr getelementptr inbounds ([3 x i32], ptr @__cpu_features2, i32 0, i32 1), align 4
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+ // CHECK-X86-NEXT: [[TMP1:%.*]] = and i32 [[TMP0]], -2147483648
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+ // CHECK-X86-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], -2147483648
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+ // CHECK-X86-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
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+ // CHECK-X86-NEXT: [[CONV:%.*]] = zext i1 [[TMP3]] to i32
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+ // CHECK-X86-NEXT: ret i32 [[CONV]]
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+ //
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int baseline () { return __builtin_cpu_supports ("x86-64" ); }
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- // CHECK-X86-LABEL: define{{.*}} @v2(
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- // CHECK-X86: [[LOAD:%.*]] = load i32, ptr getelementptr inbounds ([[[#]] x i32], ptr @__cpu_features2, i32 0, i32 2)
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- // CHECK-X86-NEXT: and i32 [[LOAD]], 1
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+ // CHECK-X86-LABEL: define dso_local i32 @v2(
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+ // CHECK-X86-SAME: ) #[[ATTR0]] {
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+ // CHECK-X86-NEXT: entry:
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+ // CHECK-X86-NEXT: [[TMP0:%.*]] = load i32, ptr getelementptr inbounds ([3 x i32], ptr @__cpu_features2, i32 0, i32 2), align 4
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+ // CHECK-X86-NEXT: [[TMP1:%.*]] = and i32 [[TMP0]], 1
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+ // CHECK-X86-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 1
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+ // CHECK-X86-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
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+ // CHECK-X86-NEXT: [[CONV:%.*]] = zext i1 [[TMP3]] to i32
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+ // CHECK-X86-NEXT: ret i32 [[CONV]]
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+ //
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int v2 () { return __builtin_cpu_supports ("x86-64-v2" ); }
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- // CHECK-X86-LABEL: define{{.*}} @v3(
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- // CHECK-X86: [[LOAD:%.*]] = load i32, ptr getelementptr inbounds ([[[#]] x i32], ptr @__cpu_features2, i32 0, i32 2)
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- // CHECK-X86-NEXT: and i32 [[LOAD]], 2
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+ // CHECK-X86-LABEL: define dso_local i32 @v3(
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+ // CHECK-X86-SAME: ) #[[ATTR0]] {
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+ // CHECK-X86-NEXT: entry:
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+ // CHECK-X86-NEXT: [[TMP0:%.*]] = load i32, ptr getelementptr inbounds ([3 x i32], ptr @__cpu_features2, i32 0, i32 2), align 4
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+ // CHECK-X86-NEXT: [[TMP1:%.*]] = and i32 [[TMP0]], 2
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+ // CHECK-X86-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 2
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+ // CHECK-X86-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
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+ // CHECK-X86-NEXT: [[CONV:%.*]] = zext i1 [[TMP3]] to i32
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+ // CHECK-X86-NEXT: ret i32 [[CONV]]
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+ //
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int v3 () { return __builtin_cpu_supports ("x86-64-v3" ); }
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- // CHECK-X86-LABEL: define{{.*}} @v4(
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- // CHECK-X86: [[LOAD:%.*]] = load i32, ptr getelementptr inbounds ([[[#]] x i32], ptr @__cpu_features2, i32 0, i32 2)
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- // CHECK-X86-NEXT: and i32 [[LOAD]], 4
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+ // CHECK-X86-LABEL: define dso_local i32 @v4(
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+ // CHECK-X86-SAME: ) #[[ATTR0]] {
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+ // CHECK-X86-NEXT: entry:
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+ // CHECK-X86-NEXT: [[TMP0:%.*]] = load i32, ptr getelementptr inbounds ([3 x i32], ptr @__cpu_features2, i32 0, i32 2), align 4
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+ // CHECK-X86-NEXT: [[TMP1:%.*]] = and i32 [[TMP0]], 4
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+ // CHECK-X86-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 4
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+ // CHECK-X86-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
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+ // CHECK-X86-NEXT: [[CONV:%.*]] = zext i1 [[TMP3]] to i32
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+ // CHECK-X86-NEXT: ret i32 [[CONV]]
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+ //
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int v4 () { return __builtin_cpu_supports ("x86-64-v4" ); }
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#else
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+ // CHECK-PPC-LABEL: define dso_local signext i32 @test(
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+ // CHECK-PPC-SAME: i32 noundef signext [[A:%.*]]) #[[ATTR0:[0-9]+]] {
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+ // CHECK-PPC-NEXT: entry:
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+ // CHECK-PPC-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
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+ // CHECK-PPC-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
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+ // CHECK-PPC-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
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+ // CHECK-PPC-NEXT: [[CPU_SUPPORTS:%.*]] = call i32 @llvm.ppc.fixed.addr.ld(i32 2)
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+ // CHECK-PPC-NEXT: [[TMP0:%.*]] = and i32 [[CPU_SUPPORTS]], 8388608
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+ // CHECK-PPC-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0
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+ // CHECK-PPC-NEXT: br i1 [[TMP1]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]
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+ // CHECK-PPC: if.then:
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+ // CHECK-PPC-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_ADDR]], align 4
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+ // CHECK-PPC-NEXT: store i32 [[TMP2]], ptr [[RETVAL]], align 4
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+ // CHECK-PPC-NEXT: br label [[RETURN:%.*]]
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+ // CHECK-PPC: if.else:
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+ // CHECK-PPC-NEXT: [[CPU_SUPPORTS1:%.*]] = call i32 @llvm.ppc.fixed.addr.ld(i32 1)
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+ // CHECK-PPC-NEXT: [[TMP3:%.*]] = and i32 [[CPU_SUPPORTS1]], 67108864
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+ // CHECK-PPC-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
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+ // CHECK-PPC-NEXT: br i1 [[TMP4]], label [[IF_THEN2:%.*]], label [[IF_ELSE3:%.*]]
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+ // CHECK-PPC: if.then2:
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+ // CHECK-PPC-NEXT: [[TMP5:%.*]] = load i32, ptr [[A_ADDR]], align 4
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+ // CHECK-PPC-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 5
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+ // CHECK-PPC-NEXT: store i32 [[SUB]], ptr [[RETVAL]], align 4
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+ // CHECK-PPC-NEXT: br label [[RETURN]]
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+ // CHECK-PPC: if.else3:
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+ // CHECK-PPC-NEXT: [[CPU_IS:%.*]] = call i32 @llvm.ppc.fixed.addr.ld(i32 3)
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+ // CHECK-PPC-NEXT: [[TMP6:%.*]] = icmp eq i32 [[CPU_IS]], 39
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+ // CHECK-PPC-NEXT: br i1 [[TMP6]], label [[IF_THEN4:%.*]], label [[IF_END:%.*]]
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+ // CHECK-PPC: if.then4:
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+ // CHECK-PPC-NEXT: [[TMP7:%.*]] = load i32, ptr [[A_ADDR]], align 4
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+ // CHECK-PPC-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
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+ // CHECK-PPC-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], [[TMP8]]
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+ // CHECK-PPC-NEXT: store i32 [[ADD]], ptr [[RETVAL]], align 4
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+ // CHECK-PPC-NEXT: br label [[RETURN]]
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+ // CHECK-PPC: if.end:
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+ // CHECK-PPC-NEXT: br label [[IF_END5:%.*]]
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+ // CHECK-PPC: if.end5:
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+ // CHECK-PPC-NEXT: br label [[IF_END6:%.*]]
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+ // CHECK-PPC: if.end6:
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+ // CHECK-PPC-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4
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+ // CHECK-PPC-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP9]], 5
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+ // CHECK-PPC-NEXT: store i32 [[ADD7]], ptr [[RETVAL]], align 4
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+ // CHECK-PPC-NEXT: br label [[RETURN]]
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+ // CHECK-PPC: return:
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+ // CHECK-PPC-NEXT: [[TMP10:%.*]] = load i32, ptr [[RETVAL]], align 4
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+ // CHECK-PPC-NEXT: ret i32 [[TMP10]]
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+ //
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int test (int a ) {
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- // CHECK-PPC: [[CPUSUP:%[^ ]+]] = call i32 @llvm.ppc.fixed.addr.ld(i32 2)
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- // CHECK-PPC: [[AND:%[^ ]+]] = and i32 [[CPUSUP]], 8388608
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- // CHECK-PPC: icmp ne i32 [[AND]], 0
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- // CHECK-PPC: [[CPUSUP2:%[^ ]+]] = call i32 @llvm.ppc.fixed.addr.ld(i32 1)
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- // CHECK-PPC: [[AND2:%[^ ]+]] = and i32 [[CPUSUP2]], 67108864
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- // CHECK-PPC: icmp ne i32 [[AND2]], 0
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- // CHECK-PPC: [[CPUID:%[^ ]+]] = call i32 @llvm.ppc.fixed.addr.ld(i32 3)
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- // CHECK-PPC: icmp eq i32 [[CPUID]], 39
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if (__builtin_cpu_supports ("arch_3_00" )) // HWCAP2
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return a ;
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else if (__builtin_cpu_supports ("mmu" )) // HWCAP
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