Address comments

- Use script for generating test checks
- Clean up code and rename macros for clarity
- Remove magic number offsets
- Get rid of auxiliary targets in Sema checking
- Clarify some comments and add missing ones
- Add check for undefined symbol added for safety

Author: Nemanja Ivanovic

clang/lib/Basic/Targets/PPC.cpp

@@ -875,14 +875,14 @@ ArrayRef<Builtin::Info> PPCTargetInfo::getTargetBuiltins() const {
 }
 
 bool PPCTargetInfo::validateCpuSupports(StringRef FeatureStr) const {
-#define PPC_FEATURE(NAME, DESC, ENUMNAME, ENUMVAL, HWCAPN) .Case(NAME, true)
+#define PPC_LNX_FEATURE(NAME, DESC, ENUMNAME, ENUMVAL, HWCAPN) .Case(NAME, true)
   return llvm::StringSwitch<bool>(FeatureStr)
 #include "llvm/TargetParser/PPCTargetParser.def"
       .Default(false);
 }
 
 bool PPCTargetInfo::validateCpuIs(StringRef CPUName) const {
-#define PPC_CPU(NAME, NUM) .Case(NAME, true)
+#define PPC_LNX_CPU(NAME, NUM) .Case(NAME, true)
   return llvm::StringSwitch<bool>(CPUName)
 #include "llvm/TargetParser/PPCTargetParser.def"
       .Default(false);

clang/lib/CodeGen/CGBuiltin.cpp

@@ -16090,7 +16090,7 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned BuiltinID,
     const Expr *CPUExpr = E->getArg(0)->IgnoreParenCasts();
     StringRef CPUStr = cast<clang::StringLiteral>(CPUExpr)->getString();
     unsigned NumCPUID = StringSwitch<unsigned>(CPUStr)
-#define PPC_CPU(Name, NumericID) .Case(Name, NumericID)
+#define PPC_LNX_CPU(Name, NumericID) .Case(Name, NumericID)
 #include "llvm/TargetParser/PPCTargetParser.def"
                             .Default(-1U);
     Value *Op0 = llvm::ConstantInt::get(Int32Ty, PPC_FAWORD_CPUID);
@@ -16106,7 +16106,7 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned BuiltinID,
     StringRef CPUStr = cast<clang::StringLiteral>(CPUExpr)->getString();
     std::tie(FeatureWord, BitMask) =
         StringSwitch<std::pair<unsigned, unsigned>>(CPUStr)
-#define PPC_FEATURE(Name, Description, EnumName, Bitmask, FA_WORD)             \
+#define PPC_LNX_FEATURE(Name, Description, EnumName, Bitmask, FA_WORD)         \
   .Case(Name, {FA_WORD, Bitmask})
 #include "llvm/TargetParser/PPCTargetParser.def"
             .Default({0, 0});

clang/lib/Sema/SemaChecking.cpp

@@ -2110,61 +2110,35 @@ static bool checkFPMathBuiltinElementType(Sema &S, SourceLocation Loc,
   return false;
 }
 
-/// SemaBuiltinCpuSupports - Handle __builtin_cpu_supports(char *).
-/// This checks that the target supports __builtin_cpu_supports and
-/// that the string argument is constant and valid.
-static bool SemaBuiltinCpuSupports(Sema &S, const TargetInfo &TI,
-                                   const TargetInfo *AuxTI, CallExpr *TheCall) {
-  Expr *Arg = TheCall->getArg(0);
-
-  const TargetInfo *TheTI = nullptr;
-  if (TI.supportsCpuSupports())
-    TheTI = &TI;
-  else if (AuxTI && AuxTI->supportsCpuSupports())
-    TheTI = AuxTI;
-  else
+/// SemaBuiltinCpu{Supports|Is} - Handle __builtin_cpu_{supports|is}(char *).
+/// This checks that the target supports the builtin and that the string
+/// argument is constant and valid.
+static bool SemaBuiltinCpu(Sema &S, const TargetInfo &TI, CallExpr *TheCall,
+                           unsigned BuiltinID) {
+  assert((BuiltinID == Builtin::BI__builtin_cpu_supports ||
+          BuiltinID == Builtin::BI__builtin_cpu_is) &&
+         "Expecting __builtin_cpu_...");
+
+  bool IsCPUSupports = BuiltinID == Builtin::BI__builtin_cpu_supports;
+  if (IsCPUSupports && !TI.supportsCpuSupports())
     return S.Diag(TheCall->getBeginLoc(), diag::err_builtin_target_unsupported)
            << SourceRange(TheCall->getBeginLoc(), TheCall->getEndLoc());
-
-  // Check if the argument is a string literal.
-  if (!isa<StringLiteral>(Arg->IgnoreParenImpCasts()))
-    return S.Diag(TheCall->getBeginLoc(), diag::err_expr_not_string_literal)
-           << Arg->getSourceRange();
-
-  // Check the contents of the string.
-  StringRef Feature =
-      cast<StringLiteral>(Arg->IgnoreParenImpCasts())->getString();
-  if (!TheTI->validateCpuSupports(Feature))
-    return S.Diag(TheCall->getBeginLoc(), diag::err_invalid_cpu_supports)
-           << Arg->getSourceRange();
-  return false;
-}
-
-/// SemaBuiltinCpuIs - Handle __builtin_cpu_is(char *).
-/// This checks that the target supports __builtin_cpu_is and
-/// that the string argument is constant and valid.
-static bool SemaBuiltinCpuIs(Sema &S, const TargetInfo &TI,
-                             const TargetInfo *AuxTI, CallExpr *TheCall) {
-  Expr *Arg = TheCall->getArg(0);
-
-  const TargetInfo *TheTI = nullptr;
-  if (TI.supportsCpuIs())
-    TheTI = &TI;
-  else if (AuxTI && AuxTI->supportsCpuIs())
-    TheTI = AuxTI;
-  else
+  if (!IsCPUSupports && !TI.supportsCpuIs())
     return S.Diag(TheCall->getBeginLoc(), diag::err_builtin_target_unsupported)
            << SourceRange(TheCall->getBeginLoc(), TheCall->getEndLoc());
 
+  Expr *Arg = TheCall->getArg(0)->IgnoreParenImpCasts();
   // Check if the argument is a string literal.
-  if (!isa<StringLiteral>(Arg->IgnoreParenImpCasts()))
+  if (!isa<StringLiteral>(Arg))
     return S.Diag(TheCall->getBeginLoc(), diag::err_expr_not_string_literal)
            << Arg->getSourceRange();
 
   // Check the contents of the string.
-  StringRef Feature =
-      cast<StringLiteral>(Arg->IgnoreParenImpCasts())->getString();
-  if (!TheTI->validateCpuIs(Feature))
+  StringRef Feature = cast<StringLiteral>(Arg)->getString();
+  if (IsCPUSupports && !TI.validateCpuSupports(Feature))
+    return S.Diag(TheCall->getBeginLoc(), diag::err_invalid_cpu_supports)
+           << Arg->getSourceRange();
+  if (!IsCPUSupports && !TI.validateCpuIs(Feature))
     return S.Diag(TheCall->getBeginLoc(), diag::err_invalid_cpu_is)
            << Arg->getSourceRange();
   return false;
@@ -2198,13 +2172,8 @@ Sema::CheckBuiltinFunctionCall(FunctionDecl *FDecl, unsigned BuiltinID,
 
   switch (BuiltinID) {
   case Builtin::BI__builtin_cpu_supports:
-    if (SemaBuiltinCpuSupports(*this, Context.getTargetInfo(),
-                               Context.getAuxTargetInfo(), TheCall))
-      return ExprError();
-    break;
   case Builtin::BI__builtin_cpu_is:
-    if (SemaBuiltinCpuIs(*this, Context.getTargetInfo(),
-                         Context.getAuxTargetInfo(), TheCall))
+    if (SemaBuiltinCpu(*this, Context.getTargetInfo(), TheCall, BuiltinID))
       return ExprError();
     break;
   case Builtin::BI__builtin_cpu_init:

clang/test/CodeGen/builtin-cpu-supports.c

@@ -1,6 +1,7 @@
-// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -emit-llvm < %s | FileCheck %s \
-// RUN:   --check-prefix=CHECK-X86
-// RUN: %clang_cc1 -triple ppc64le-linux-gnu -emit-llvm < %s | FileCheck %s \
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 3
+// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -emit-llvm -o - %s | \
+// RUN:   FileCheck %s --check-prefix=CHECK-X86
+// RUN: %clang_cc1 -triple ppc64le-linux-gnu -emit-llvm -o - %s | FileCheck %s \
 // RUN:   --check-prefix=CHECK-PPC
 
 #ifndef __PPC__
@@ -9,9 +10,33 @@
 // global, the bit grab, and the icmp correct.
 extern void a(const char *);
 
-// CHECK-X86: @__cpu_model = external dso_local global { i32, i32, i32, [1 x i32] }
-// CHECK-X86: @__cpu_features2 = external dso_local global [3 x i32]
 
+// CHECK-X86-LABEL: define dso_local i32 @main(
+// CHECK-X86-SAME: ) #[[ATTR0:[0-9]+]] {
+// CHECK-X86-NEXT:  entry:
+// CHECK-X86-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
+// CHECK-X86-NEXT:    store i32 0, ptr [[RETVAL]], align 4
+// CHECK-X86-NEXT:    call void @__cpu_indicator_init()
+// CHECK-X86-NEXT:    [[TMP0:%.*]] = load i32, ptr getelementptr inbounds ({ i32, i32, i32, [1 x i32] }, ptr @__cpu_model, i32 0, i32 3, i32 0), align 4
+// CHECK-X86-NEXT:    [[TMP1:%.*]] = and i32 [[TMP0]], 256
+// CHECK-X86-NEXT:    [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 256
+// CHECK-X86-NEXT:    [[TMP3:%.*]] = and i1 true, [[TMP2]]
+// CHECK-X86-NEXT:    br i1 [[TMP3]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
+// CHECK-X86:       if.then:
+// CHECK-X86-NEXT:    call void @a(ptr noundef @.str)
+// CHECK-X86-NEXT:    br label [[IF_END]]
+// CHECK-X86:       if.end:
+// CHECK-X86-NEXT:    [[TMP4:%.*]] = load i32, ptr @__cpu_features2, align 4
+// CHECK-X86-NEXT:    [[TMP5:%.*]] = and i32 [[TMP4]], 1
+// CHECK-X86-NEXT:    [[TMP6:%.*]] = icmp eq i32 [[TMP5]], 1
+// CHECK-X86-NEXT:    [[TMP7:%.*]] = and i1 true, [[TMP6]]
+// CHECK-X86-NEXT:    br i1 [[TMP7]], label [[IF_THEN1:%.*]], label [[IF_END2:%.*]]
+// CHECK-X86:       if.then1:
+// CHECK-X86-NEXT:    call void @a(ptr noundef @.str.1)
+// CHECK-X86-NEXT:    br label [[IF_END2]]
+// CHECK-X86:       if.end2:
+// CHECK-X86-NEXT:    ret i32 0
+//
 int main(void) {
   __builtin_cpu_init();
 
@@ -20,51 +45,111 @@ int main(void) {
   if (__builtin_cpu_supports("sse4.2"))
     a("sse4.2");
 
-  // CHECK-X86: [[LOAD:%[^ ]+]] = load i32, ptr getelementptr inbounds ({ i32, i32, i32, [1 x i32] }, ptr @__cpu_model, i32 0, i32 3, i32 0)
-  // CHECK-X86: [[AND:%[^ ]+]] = and i32 [[LOAD]], 256
-  // CHECK-X86: = icmp eq i32 [[AND]], 256
 
   if (__builtin_cpu_supports("gfni"))
     a("gfni");
 
-  // CHECK-X86: [[LOAD:%[^ ]+]] = load i32, ptr @__cpu_features2
-  // CHECK-X86: [[AND:%[^ ]+]] = and i32 [[LOAD]], 1
-  // CHECK-X86: = icmp eq i32 [[AND]], 1
 
   return 0;
 }
 
-// CHECK-X86: declare dso_local void @__cpu_indicator_init()
 
-// CHECK-X86-LABEL: define{{.*}} @baseline(
-// CHECK-X86:         [[LOAD:%.*]] = load i32, ptr getelementptr inbounds ([[[#]] x i32], ptr @__cpu_features2, i32 0, i32 1)
-// CHECK-X86-NEXT:    and i32 [[LOAD]], -2147483648
+// CHECK-X86-LABEL: define dso_local i32 @baseline(
+// CHECK-X86-SAME: ) #[[ATTR0]] {
+// CHECK-X86-NEXT:  entry:
+// CHECK-X86-NEXT:    [[TMP0:%.*]] = load i32, ptr getelementptr inbounds ([3 x i32], ptr @__cpu_features2, i32 0, i32 1), align 4
+// CHECK-X86-NEXT:    [[TMP1:%.*]] = and i32 [[TMP0]], -2147483648
+// CHECK-X86-NEXT:    [[TMP2:%.*]] = icmp eq i32 [[TMP1]], -2147483648
+// CHECK-X86-NEXT:    [[TMP3:%.*]] = and i1 true, [[TMP2]]
+// CHECK-X86-NEXT:    [[CONV:%.*]] = zext i1 [[TMP3]] to i32
+// CHECK-X86-NEXT:    ret i32 [[CONV]]
+//
 int baseline() { return __builtin_cpu_supports("x86-64"); }
 
-// CHECK-X86-LABEL: define{{.*}} @v2(
-// CHECK-X86:         [[LOAD:%.*]] = load i32, ptr getelementptr inbounds ([[[#]] x i32], ptr @__cpu_features2, i32 0, i32 2)
-// CHECK-X86-NEXT:    and i32 [[LOAD]], 1
+// CHECK-X86-LABEL: define dso_local i32 @v2(
+// CHECK-X86-SAME: ) #[[ATTR0]] {
+// CHECK-X86-NEXT:  entry:
+// CHECK-X86-NEXT:    [[TMP0:%.*]] = load i32, ptr getelementptr inbounds ([3 x i32], ptr @__cpu_features2, i32 0, i32 2), align 4
+// CHECK-X86-NEXT:    [[TMP1:%.*]] = and i32 [[TMP0]], 1
+// CHECK-X86-NEXT:    [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 1
+// CHECK-X86-NEXT:    [[TMP3:%.*]] = and i1 true, [[TMP2]]
+// CHECK-X86-NEXT:    [[CONV:%.*]] = zext i1 [[TMP3]] to i32
+// CHECK-X86-NEXT:    ret i32 [[CONV]]
+//
 int v2() { return __builtin_cpu_supports("x86-64-v2"); }
 
-// CHECK-X86-LABEL: define{{.*}} @v3(
-// CHECK-X86:         [[LOAD:%.*]] = load i32, ptr getelementptr inbounds ([[[#]] x i32], ptr @__cpu_features2, i32 0, i32 2)
-// CHECK-X86-NEXT:    and i32 [[LOAD]], 2
+// CHECK-X86-LABEL: define dso_local i32 @v3(
+// CHECK-X86-SAME: ) #[[ATTR0]] {
+// CHECK-X86-NEXT:  entry:
+// CHECK-X86-NEXT:    [[TMP0:%.*]] = load i32, ptr getelementptr inbounds ([3 x i32], ptr @__cpu_features2, i32 0, i32 2), align 4
+// CHECK-X86-NEXT:    [[TMP1:%.*]] = and i32 [[TMP0]], 2
+// CHECK-X86-NEXT:    [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 2
+// CHECK-X86-NEXT:    [[TMP3:%.*]] = and i1 true, [[TMP2]]
+// CHECK-X86-NEXT:    [[CONV:%.*]] = zext i1 [[TMP3]] to i32
+// CHECK-X86-NEXT:    ret i32 [[CONV]]
+//
 int v3() { return __builtin_cpu_supports("x86-64-v3"); }
 
-// CHECK-X86-LABEL: define{{.*}} @v4(
-// CHECK-X86:         [[LOAD:%.*]] = load i32, ptr getelementptr inbounds ([[[#]] x i32], ptr @__cpu_features2, i32 0, i32 2)
-// CHECK-X86-NEXT:    and i32 [[LOAD]], 4
+// CHECK-X86-LABEL: define dso_local i32 @v4(
+// CHECK-X86-SAME: ) #[[ATTR0]] {
+// CHECK-X86-NEXT:  entry:
+// CHECK-X86-NEXT:    [[TMP0:%.*]] = load i32, ptr getelementptr inbounds ([3 x i32], ptr @__cpu_features2, i32 0, i32 2), align 4
+// CHECK-X86-NEXT:    [[TMP1:%.*]] = and i32 [[TMP0]], 4
+// CHECK-X86-NEXT:    [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 4
+// CHECK-X86-NEXT:    [[TMP3:%.*]] = and i1 true, [[TMP2]]
+// CHECK-X86-NEXT:    [[CONV:%.*]] = zext i1 [[TMP3]] to i32
+// CHECK-X86-NEXT:    ret i32 [[CONV]]
+//
 int v4() { return __builtin_cpu_supports("x86-64-v4"); }
 #else
+// CHECK-PPC-LABEL: define dso_local signext i32 @test(
+// CHECK-PPC-SAME: i32 noundef signext [[A:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-PPC-NEXT:  entry:
+// CHECK-PPC-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
+// CHECK-PPC-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
+// CHECK-PPC-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
+// CHECK-PPC-NEXT:    [[CPU_SUPPORTS:%.*]] = call i32 @llvm.ppc.fixed.addr.ld(i32 2)
+// CHECK-PPC-NEXT:    [[TMP0:%.*]] = and i32 [[CPU_SUPPORTS]], 8388608
+// CHECK-PPC-NEXT:    [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0
+// CHECK-PPC-NEXT:    br i1 [[TMP1]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]
+// CHECK-PPC:       if.then:
+// CHECK-PPC-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A_ADDR]], align 4
+// CHECK-PPC-NEXT:    store i32 [[TMP2]], ptr [[RETVAL]], align 4
+// CHECK-PPC-NEXT:    br label [[RETURN:%.*]]
+// CHECK-PPC:       if.else:
+// CHECK-PPC-NEXT:    [[CPU_SUPPORTS1:%.*]] = call i32 @llvm.ppc.fixed.addr.ld(i32 1)
+// CHECK-PPC-NEXT:    [[TMP3:%.*]] = and i32 [[CPU_SUPPORTS1]], 67108864
+// CHECK-PPC-NEXT:    [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
+// CHECK-PPC-NEXT:    br i1 [[TMP4]], label [[IF_THEN2:%.*]], label [[IF_ELSE3:%.*]]
+// CHECK-PPC:       if.then2:
+// CHECK-PPC-NEXT:    [[TMP5:%.*]] = load i32, ptr [[A_ADDR]], align 4
+// CHECK-PPC-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP5]], 5
+// CHECK-PPC-NEXT:    store i32 [[SUB]], ptr [[RETVAL]], align 4
+// CHECK-PPC-NEXT:    br label [[RETURN]]
+// CHECK-PPC:       if.else3:
+// CHECK-PPC-NEXT:    [[CPU_IS:%.*]] = call i32 @llvm.ppc.fixed.addr.ld(i32 3)
+// CHECK-PPC-NEXT:    [[TMP6:%.*]] = icmp eq i32 [[CPU_IS]], 39
+// CHECK-PPC-NEXT:    br i1 [[TMP6]], label [[IF_THEN4:%.*]], label [[IF_END:%.*]]
+// CHECK-PPC:       if.then4:
+// CHECK-PPC-NEXT:    [[TMP7:%.*]] = load i32, ptr [[A_ADDR]], align 4
+// CHECK-PPC-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
+// CHECK-PPC-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP7]], [[TMP8]]
+// CHECK-PPC-NEXT:    store i32 [[ADD]], ptr [[RETVAL]], align 4
+// CHECK-PPC-NEXT:    br label [[RETURN]]
+// CHECK-PPC:       if.end:
+// CHECK-PPC-NEXT:    br label [[IF_END5:%.*]]
+// CHECK-PPC:       if.end5:
+// CHECK-PPC-NEXT:    br label [[IF_END6:%.*]]
+// CHECK-PPC:       if.end6:
+// CHECK-PPC-NEXT:    [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4
+// CHECK-PPC-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP9]], 5
+// CHECK-PPC-NEXT:    store i32 [[ADD7]], ptr [[RETVAL]], align 4
+// CHECK-PPC-NEXT:    br label [[RETURN]]
+// CHECK-PPC:       return:
+// CHECK-PPC-NEXT:    [[TMP10:%.*]] = load i32, ptr [[RETVAL]], align 4
+// CHECK-PPC-NEXT:    ret i32 [[TMP10]]
+//
 int test(int a) {
-// CHECK-PPC: [[CPUSUP:%[^ ]+]] = call i32 @llvm.ppc.fixed.addr.ld(i32 2)
-// CHECK-PPC: [[AND:%[^ ]+]] = and i32 [[CPUSUP]], 8388608
-// CHECK-PPC: icmp ne i32 [[AND]], 0
-// CHECK-PPC: [[CPUSUP2:%[^ ]+]] = call i32 @llvm.ppc.fixed.addr.ld(i32 1)
-// CHECK-PPC: [[AND2:%[^ ]+]] = and i32 [[CPUSUP2]], 67108864
-// CHECK-PPC: icmp ne i32 [[AND2]], 0
-// CHECK-PPC: [[CPUID:%[^ ]+]] = call i32 @llvm.ppc.fixed.addr.ld(i32 3)
-// CHECK-PPC: icmp eq i32 [[CPUID]], 39
   if (__builtin_cpu_supports("arch_3_00")) // HWCAP2
     return a;
   else if (__builtin_cpu_supports("mmu"))  // HWCAP

llvm/include/llvm/IR/IntrinsicsPowerPC.td

@@ -211,7 +211,10 @@ let TargetPrefix = "ppc" in {  // All intrinsics start with "llvm.ppc.".
             [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_vararg_ty],
             [IntrNoMem]>;
   // Load of a value provided by the system library at a fixed address. Used for
-  // accessing things like HWCAP word provided by GLIBC.
+  // accessing things like HWCAP word provided by GLIBC. The immediate argument
+  // is not an address but a value defined in
+  // include/llvm/TargetParser/PPCTargetParser.def. Each of the values provided
+  // by Glibc is a 32-bit word.
   def int_ppc_fixed_addr_ld
       : DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty],
                               [IntrInaccessibleMemOnly, ImmArg<ArgIndex<0>>]>;