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Replace TypeSize::{getFixed,getScalable} with canonical TypeSize::{Fixed,Scalable}. NFC
1 parent 58d4fe2 commit 8e247b8

23 files changed

+65
-67
lines changed

‎llvm/include/llvm/Analysis/TargetTransformInfoImpl.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -443,7 +443,7 @@ class TargetTransformInfoImplBase {
443443
}
444444

445445
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const {
446-
return TypeSize::getFixed(32);
446+
return TypeSize::Fixed(32);
447447
}
448448

449449
unsigned getMinVectorRegisterBitWidth() const { return 128; }

‎llvm/include/llvm/CodeGen/BasicTTIImpl.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -714,7 +714,7 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase<T> {
714714
/// @{
715715

716716
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const {
717-
return TypeSize::getFixed(32);
717+
return TypeSize::Fixed(32);
718718
}
719719

720720
std::optional<unsigned> getMaxVScale() const { return std::nullopt; }

‎llvm/lib/Analysis/BasicAliasAnalysis.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -111,7 +111,7 @@ static std::optional<TypeSize> getObjectSize(const Value *V,
111111
Opts.RoundToAlign = RoundToAlign;
112112
Opts.NullIsUnknownSize = NullIsValidLoc;
113113
if (getObjectSize(V, Size, DL, &TLI, Opts))
114-
return TypeSize::getFixed(Size);
114+
return TypeSize::Fixed(Size);
115115
return std::nullopt;
116116
}
117117

@@ -177,7 +177,7 @@ static TypeSize getMinimalExtentFrom(const Value &V,
177177
// accessed, thus valid.
178178
if (LocSize.isPrecise())
179179
DerefBytes = std::max(DerefBytes, LocSize.getValue().getKnownMinValue());
180-
return TypeSize::getFixed(DerefBytes);
180+
return TypeSize::Fixed(DerefBytes);
181181
}
182182

183183
/// Returns true if we can prove that the object specified by V has size Size.

‎llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4422,7 +4422,7 @@ void DAGTypeLegalizer::ExpandIntRes_ShiftThroughStack(SDNode *N, SDValue &Lo,
44224422
// FIXME: should we be more picky about alignment?
44234423
Align StackSlotAlignment(1);
44244424
SDValue StackPtr = DAG.CreateStackTemporary(
4425-
TypeSize::getFixed(StackSlotByteWidth), StackSlotAlignment);
4425+
TypeSize::Fixed(StackSlotByteWidth), StackSlotAlignment);
44264426
EVT PtrTy = StackPtr.getValueType();
44274427
SDValue Ch = DAG.getEntryNode();
44284428

‎llvm/lib/IR/DebugInfo.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1947,7 +1947,7 @@ std::optional<AssignmentInfo> at::getAssignmentInfo(const DataLayout &DL,
19471947
// We can't use a non-const size, bail.
19481948
return std::nullopt;
19491949
uint64_t SizeInBits = 8 * ConstLengthInBytes->getZExtValue();
1950-
return getAssignmentInfoImpl(DL, StoreDest, TypeSize::getFixed(SizeInBits));
1950+
return getAssignmentInfoImpl(DL, StoreDest, TypeSize::Fixed(SizeInBits));
19511951
}
19521952

19531953
std::optional<AssignmentInfo> at::getAssignmentInfo(const DataLayout &DL,

‎llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp

Lines changed: 6 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1961,21 +1961,20 @@ TypeSize
19611961
AArch64TTIImpl::getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const {
19621962
switch (K) {
19631963
case TargetTransformInfo::RGK_Scalar:
1964-
return TypeSize::getFixed(64);
1964+
return TypeSize::Fixed(64);
19651965
case TargetTransformInfo::RGK_FixedWidthVector:
19661966
if (!ST->isNeonAvailable() && !EnableFixedwidthAutovecInStreamingMode)
1967-
return TypeSize::getFixed(0);
1967+
return TypeSize::Fixed(0);
19681968

19691969
if (ST->hasSVE())
1970-
return TypeSize::getFixed(
1971-
std::max(ST->getMinSVEVectorSizeInBits(), 128u));
1970+
return TypeSize::Fixed(std::max(ST->getMinSVEVectorSizeInBits(), 128u));
19721971

1973-
return TypeSize::getFixed(ST->hasNEON() ? 128 : 0);
1972+
return TypeSize::Fixed(ST->hasNEON() ? 128 : 0);
19741973
case TargetTransformInfo::RGK_ScalableVector:
19751974
if (!ST->isSVEAvailable() && !EnableScalableAutovecInStreamingMode)
1976-
return TypeSize::getScalable(0);
1975+
return TypeSize::Scalable(0);
19771976

1978-
return TypeSize::getScalable(ST->hasSVE() ? 128 : 0);
1977+
return TypeSize::Scalable(ST->hasSVE() ? 128 : 0);
19791978
}
19801979
llvm_unreachable("Unsupported register kind");
19811980
}

‎llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -321,11 +321,11 @@ TypeSize
321321
GCNTTIImpl::getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const {
322322
switch (K) {
323323
case TargetTransformInfo::RGK_Scalar:
324-
return TypeSize::getFixed(32);
324+
return TypeSize::Fixed(32);
325325
case TargetTransformInfo::RGK_FixedWidthVector:
326-
return TypeSize::getFixed(ST->hasPackedFP32Ops() ? 64 : 32);
326+
return TypeSize::Fixed(ST->hasPackedFP32Ops() ? 64 : 32);
327327
case TargetTransformInfo::RGK_ScalableVector:
328-
return TypeSize::getScalable(0);
328+
return TypeSize::Scalable(0);
329329
}
330330
llvm_unreachable("Unsupported register kind");
331331
}

‎llvm/lib/Target/AMDGPU/R600TargetTransformInfo.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -38,7 +38,7 @@ unsigned R600TTIImpl::getNumberOfRegisters(bool Vec) const {
3838

3939
TypeSize
4040
R600TTIImpl::getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const {
41-
return TypeSize::getFixed(32);
41+
return TypeSize::Fixed(32);
4242
}
4343

4444
unsigned R600TTIImpl::getMinVectorRegisterBitWidth() const { return 32; }

‎llvm/lib/Target/ARM/ARMTargetTransformInfo.h

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -165,15 +165,15 @@ class ARMTTIImpl : public BasicTTIImplBase<ARMTTIImpl> {
165165
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const {
166166
switch (K) {
167167
case TargetTransformInfo::RGK_Scalar:
168-
return TypeSize::getFixed(32);
168+
return TypeSize::Fixed(32);
169169
case TargetTransformInfo::RGK_FixedWidthVector:
170170
if (ST->hasNEON())
171-
return TypeSize::getFixed(128);
171+
return TypeSize::Fixed(128);
172172
if (ST->hasMVEIntegerOps())
173-
return TypeSize::getFixed(128);
174-
return TypeSize::getFixed(0);
173+
return TypeSize::Fixed(128);
174+
return TypeSize::Fixed(0);
175175
case TargetTransformInfo::RGK_ScalableVector:
176-
return TypeSize::getScalable(0);
176+
return TypeSize::Scalable(0);
177177
}
178178
llvm_unreachable("Unsupported register kind");
179179
}

‎llvm/lib/Target/DirectX/CBufferDataLayout.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -76,12 +76,12 @@ TypeSize LegacyCBufferLayout::getTypeAllocSize(Type *Ty) {
7676
} else if (auto *AT = dyn_cast<ArrayType>(Ty)) {
7777
unsigned NumElts = AT->getNumElements();
7878
if (NumElts == 0)
79-
return TypeSize::getFixed(0);
79+
return TypeSize::Fixed(0);
8080

8181
TypeSize EltSize = getTypeAllocSize(AT->getElementType());
8282
TypeSize AlignedEltSize = alignTo4Dwords(EltSize);
8383
// Each new element start 4 dwords aligned.
84-
return TypeSize::getFixed(AlignedEltSize * (NumElts - 1) + EltSize);
84+
return TypeSize::Fixed(AlignedEltSize * (NumElts - 1) + EltSize);
8585
} else {
8686
// NOTE: Use type store size, not align to ABI on basic types for legacy
8787
// layout.

‎llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -118,11 +118,11 @@ TypeSize
118118
HexagonTTIImpl::getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const {
119119
switch (K) {
120120
case TargetTransformInfo::RGK_Scalar:
121-
return TypeSize::getFixed(32);
121+
return TypeSize::Fixed(32);
122122
case TargetTransformInfo::RGK_FixedWidthVector:
123-
return TypeSize::getFixed(getMinVectorRegisterBitWidth());
123+
return TypeSize::Fixed(getMinVectorRegisterBitWidth());
124124
case TargetTransformInfo::RGK_ScalableVector:
125-
return TypeSize::getScalable(0);
125+
return TypeSize::Scalable(0);
126126
}
127127

128128
llvm_unreachable("Unsupported register kind");

‎llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -78,7 +78,7 @@ class NVPTXTTIImpl : public BasicTTIImplBase<NVPTXTTIImpl> {
7878
// Only <2 x half> should be vectorized, so always return 32 for the vector
7979
// register size.
8080
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const {
81-
return TypeSize::getFixed(32);
81+
return TypeSize::Fixed(32);
8282
}
8383
unsigned getMinVectorRegisterBitWidth() const { return 32; }
8484

‎llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -493,11 +493,11 @@ TypeSize
493493
PPCTTIImpl::getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const {
494494
switch (K) {
495495
case TargetTransformInfo::RGK_Scalar:
496-
return TypeSize::getFixed(ST->isPPC64() ? 64 : 32);
496+
return TypeSize::Fixed(ST->isPPC64() ? 64 : 32);
497497
case TargetTransformInfo::RGK_FixedWidthVector:
498-
return TypeSize::getFixed(ST->hasAltivec() ? 128 : 0);
498+
return TypeSize::Fixed(ST->hasAltivec() ? 128 : 0);
499499
case TargetTransformInfo::RGK_ScalableVector:
500-
return TypeSize::getScalable(0);
500+
return TypeSize::Scalable(0);
501501
}
502502

503503
llvm_unreachable("Unsupported register kind");

‎llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp

Lines changed: 6 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -210,16 +210,15 @@ RISCVTTIImpl::getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const {
210210
llvm::bit_floor(std::clamp<unsigned>(RVVRegisterWidthLMUL, 1, 8));
211211
switch (K) {
212212
case TargetTransformInfo::RGK_Scalar:
213-
return TypeSize::getFixed(ST->getXLen());
213+
return TypeSize::Fixed(ST->getXLen());
214214
case TargetTransformInfo::RGK_FixedWidthVector:
215-
return TypeSize::getFixed(
215+
return TypeSize::Fixed(
216216
ST->useRVVForFixedLengthVectors() ? LMUL * ST->getRealMinVLen() : 0);
217217
case TargetTransformInfo::RGK_ScalableVector:
218-
return TypeSize::getScalable(
219-
(ST->hasVInstructions() &&
220-
ST->getRealMinVLen() >= RISCV::RVVBitsPerBlock)
221-
? LMUL * RISCV::RVVBitsPerBlock
222-
: 0);
218+
return TypeSize::Scalable((ST->hasVInstructions() &&
219+
ST->getRealMinVLen() >= RISCV::RVVBitsPerBlock)
220+
? LMUL * RISCV::RVVBitsPerBlock
221+
: 0);
223222
}
224223

225224
llvm_unreachable("Unsupported register kind");

‎llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -366,11 +366,11 @@ TypeSize
366366
SystemZTTIImpl::getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const {
367367
switch (K) {
368368
case TargetTransformInfo::RGK_Scalar:
369-
return TypeSize::getFixed(64);
369+
return TypeSize::Fixed(64);
370370
case TargetTransformInfo::RGK_FixedWidthVector:
371-
return TypeSize::getFixed(ST->hasVector() ? 128 : 0);
371+
return TypeSize::Fixed(ST->hasVector() ? 128 : 0);
372372
case TargetTransformInfo::RGK_ScalableVector:
373-
return TypeSize::getScalable(0);
373+
return TypeSize::Scalable(0);
374374
}
375375

376376
llvm_unreachable("Unsupported register kind");

‎llvm/lib/Target/VE/VETargetTransformInfo.h

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -98,12 +98,12 @@ class VETTIImpl : public BasicTTIImplBase<VETTIImpl> {
9898
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const {
9999
switch (K) {
100100
case TargetTransformInfo::RGK_Scalar:
101-
return TypeSize::getFixed(64);
101+
return TypeSize::Fixed(64);
102102
case TargetTransformInfo::RGK_FixedWidthVector:
103103
// TODO report vregs once vector isel is stable.
104-
return TypeSize::getFixed(0);
104+
return TypeSize::Fixed(0);
105105
case TargetTransformInfo::RGK_ScalableVector:
106-
return TypeSize::getScalable(0);
106+
return TypeSize::Scalable(0);
107107
}
108108

109109
llvm_unreachable("Unsupported register kind");

‎llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -40,11 +40,11 @@ TypeSize WebAssemblyTTIImpl::getRegisterBitWidth(
4040
TargetTransformInfo::RegisterKind K) const {
4141
switch (K) {
4242
case TargetTransformInfo::RGK_Scalar:
43-
return TypeSize::getFixed(64);
43+
return TypeSize::Fixed(64);
4444
case TargetTransformInfo::RGK_FixedWidthVector:
45-
return TypeSize::getFixed(getST()->hasSIMD128() ? 128 : 64);
45+
return TypeSize::Fixed(getST()->hasSIMD128() ? 128 : 64);
4646
case TargetTransformInfo::RGK_ScalableVector:
47-
return TypeSize::getScalable(0);
47+
return TypeSize::Scalable(0);
4848
}
4949

5050
llvm_unreachable("Unsupported register kind");

‎llvm/lib/Target/X86/X86TargetTransformInfo.cpp

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -178,17 +178,17 @@ X86TTIImpl::getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const {
178178
unsigned PreferVectorWidth = ST->getPreferVectorWidth();
179179
switch (K) {
180180
case TargetTransformInfo::RGK_Scalar:
181-
return TypeSize::getFixed(ST->is64Bit() ? 64 : 32);
181+
return TypeSize::Fixed(ST->is64Bit() ? 64 : 32);
182182
case TargetTransformInfo::RGK_FixedWidthVector:
183183
if (ST->hasAVX512() && ST->hasEVEX512() && PreferVectorWidth >= 512)
184-
return TypeSize::getFixed(512);
184+
return TypeSize::Fixed(512);
185185
if (ST->hasAVX() && PreferVectorWidth >= 256)
186-
return TypeSize::getFixed(256);
186+
return TypeSize::Fixed(256);
187187
if (ST->hasSSE1() && PreferVectorWidth >= 128)
188-
return TypeSize::getFixed(128);
189-
return TypeSize::getFixed(0);
188+
return TypeSize::Fixed(128);
189+
return TypeSize::Fixed(0);
190190
case TargetTransformInfo::RGK_ScalableVector:
191-
return TypeSize::getScalable(0);
191+
return TypeSize::Scalable(0);
192192
}
193193

194194
llvm_unreachable("Unsupported register kind");

‎llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -214,7 +214,7 @@ static std::optional<TypeSize> getPointerSize(const Value *V,
214214
Opts.NullIsUnknownSize = NullPointerIsDefined(F);
215215

216216
if (getObjectSize(V, Size, DL, &TLI, Opts))
217-
return TypeSize::getFixed(Size);
217+
return TypeSize::Fixed(Size);
218218
return std::nullopt;
219219
}
220220

‎llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1720,7 +1720,7 @@ bool MemCpyOptPass::processMemCpy(MemCpyInst *M, BasicBlock::iterator &BBI) {
17201720
if (auto *CopySize = dyn_cast<ConstantInt>(M->getLength())) {
17211721
if (auto *C = dyn_cast<CallInst>(MI)) {
17221722
if (performCallSlotOptzn(M, M, M->getDest(), M->getSource(),
1723-
TypeSize::getFixed(CopySize->getZExtValue()),
1723+
TypeSize::Fixed(CopySize->getZExtValue()),
17241724
M->getDestAlign().valueOrOne(), BAA,
17251725
[C]() -> CallInst * { return C; })) {
17261726
LLVM_DEBUG(dbgs() << "Performed call slot optimization:\n"
@@ -1766,7 +1766,7 @@ bool MemCpyOptPass::processMemCpy(MemCpyInst *M, BasicBlock::iterator &BBI) {
17661766
if (Len == nullptr)
17671767
return false;
17681768
if (performStackMoveOptzn(M, M, DestAlloca, SrcAlloca,
1769-
TypeSize::getFixed(Len->getZExtValue()), BAA)) {
1769+
TypeSize::Fixed(Len->getZExtValue()), BAA)) {
17701770
// Avoid invalidating the iterator.
17711771
BBI = M->getNextNonDebugInstruction()->getIterator();
17721772
eraseInstruction(M);
@@ -1829,7 +1829,7 @@ bool MemCpyOptPass::processByValArgument(CallBase &CB, unsigned ArgNo) {
18291829
// The length of the memcpy must be larger or equal to the size of the byval.
18301830
auto *C1 = dyn_cast<ConstantInt>(MDep->getLength());
18311831
if (!C1 || !TypeSize::isKnownGE(
1832-
TypeSize::getFixed(C1->getValue().getZExtValue()), ByValSize))
1832+
TypeSize::Fixed(C1->getValue().getZExtValue()), ByValSize))
18331833
return false;
18341834

18351835
// Get the alignment of the byval. If the call doesn't specify the alignment,

‎llvm/lib/Transforms/Utils/Local.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1497,7 +1497,7 @@ static bool valueCoversEntireFragment(Type *ValTy, DbgVariableIntrinsic *DII) {
14971497
const DataLayout &DL = DII->getModule()->getDataLayout();
14981498
TypeSize ValueSize = DL.getTypeAllocSizeInBits(ValTy);
14991499
if (std::optional<uint64_t> FragmentSize = DII->getFragmentSizeInBits())
1500-
return TypeSize::isKnownGE(ValueSize, TypeSize::getFixed(*FragmentSize));
1500+
return TypeSize::isKnownGE(ValueSize, TypeSize::Fixed(*FragmentSize));
15011501

15021502
// We can't always calculate the size of the DI variable (e.g. if it is a
15031503
// VLA). Try to use the size of the alloca that the dbg intrinsic describes

‎llvm/unittests/CodeGen/LowLevelTypeTest.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -382,8 +382,8 @@ static_assert(CEV2P1.isVector());
382382
static_assert(CEV2P1.getElementCount() == ElementCount::getFixed(2));
383383
static_assert(CEV2P1.getElementCount() != ElementCount::getFixed(1));
384384
static_assert(CEV2S32.getElementCount() == ElementCount::getFixed(2));
385-
static_assert(CEV2S32.getSizeInBits() == TypeSize::getFixed(64));
386-
static_assert(CEV2P1.getSizeInBits() == TypeSize::getFixed(128));
385+
static_assert(CEV2S32.getSizeInBits() == TypeSize::Fixed(64));
386+
static_assert(CEV2P1.getSizeInBits() == TypeSize::Fixed(128));
387387
static_assert(CEV2P1.getScalarType() == LLT::pointer(1, 64));
388388
static_assert(CES32.getScalarType() == CES32);
389389
static_assert(CEV2S32.getScalarType() == CES32);

‎llvm/unittests/IR/InstructionsTest.cpp

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1746,14 +1746,14 @@ TEST(InstructionsTest, AllocaInst) {
17461746
AllocaInst &F = cast<AllocaInst>(*It++);
17471747
AllocaInst &G = cast<AllocaInst>(*It++);
17481748
AllocaInst &H = cast<AllocaInst>(*It++);
1749-
EXPECT_EQ(A.getAllocationSizeInBits(DL), TypeSize::getFixed(32));
1750-
EXPECT_EQ(B.getAllocationSizeInBits(DL), TypeSize::getFixed(128));
1749+
EXPECT_EQ(A.getAllocationSizeInBits(DL), TypeSize::Fixed(32));
1750+
EXPECT_EQ(B.getAllocationSizeInBits(DL), TypeSize::Fixed(128));
17511751
EXPECT_FALSE(C.getAllocationSizeInBits(DL));
1752-
EXPECT_EQ(D.getAllocationSizeInBits(DL), TypeSize::getFixed(512));
1753-
EXPECT_EQ(E.getAllocationSizeInBits(DL), TypeSize::getScalable(512));
1754-
EXPECT_EQ(F.getAllocationSizeInBits(DL), TypeSize::getFixed(32));
1755-
EXPECT_EQ(G.getAllocationSizeInBits(DL), TypeSize::getFixed(768));
1756-
EXPECT_EQ(H.getAllocationSizeInBits(DL), TypeSize::getFixed(160));
1752+
EXPECT_EQ(D.getAllocationSizeInBits(DL), TypeSize::Fixed(512));
1753+
EXPECT_EQ(E.getAllocationSizeInBits(DL), TypeSize::Scalable(512));
1754+
EXPECT_EQ(F.getAllocationSizeInBits(DL), TypeSize::Fixed(32));
1755+
EXPECT_EQ(G.getAllocationSizeInBits(DL), TypeSize::Fixed(768));
1756+
EXPECT_EQ(H.getAllocationSizeInBits(DL), TypeSize::Fixed(160));
17571757
}
17581758

17591759
TEST(InstructionsTest, InsertAtBegin) {

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