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[RISCV] Update MicroOpBufferSize in P400 & P600 scheduling models (#128786)
The numbers we previously picked for MicroOpBufferSize in both P400 and P600's scheduling models turned out to be too conservative and didn't properly reflect the characteristics of our microarchitectures. This patch updates these numbers to be more faithful to our hardware. This is unlikely to have any significant impact on MachineScheduler as it only uses MicroOpBufferSize in few places. That said, it is supposed to improve the accuracy of llvm-mca.
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llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -119,7 +119,7 @@ class SiFiveP400VSM3CCycles<string mx> {
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def SiFiveP400Model : SchedMachineModel {
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let IssueWidth = 3; // 3 micro-ops are dispatched per cycle.
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let MicroOpBufferSize = 56; // Max micro-ops that can be buffered.
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let MicroOpBufferSize = 96; // Max micro-ops that can be buffered.
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let LoadLatency = 4; // Cycles for loads to access the cache.
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let MispredictPenalty = 9; // Extra cycles for a mispredicted branch.
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let UnsupportedFeatures = [HasStdExtZbkb, HasStdExtZbkc, HasStdExtZbkx,

llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -286,10 +286,10 @@ class SiFiveP600VSHA2MSCycles<string mx, int sew> {
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// SiFiveP600 machine model for scheduling and other instruction cost heuristics.
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def SiFiveP600Model : SchedMachineModel {
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let IssueWidth = 4; // 4 micro-ops are dispatched per cycle.
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let MicroOpBufferSize = 160; // Max micro-ops that can be buffered.
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let LoadLatency = 4; // Cycles for loads to access the cache.
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let MispredictPenalty = 9; // Extra cycles for a mispredicted branch.
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let IssueWidth = 4; // 4 micro-ops are dispatched per cycle.
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let MicroOpBufferSize = 192; // Max micro-ops that can be buffered.
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let LoadLatency = 4; // Cycles for loads to access the cache.
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let MispredictPenalty = 9; // Extra cycles for a mispredicted branch.
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let UnsupportedFeatures = [HasStdExtZbkb, HasStdExtZbkc, HasStdExtZbkx,
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HasStdExtZknd, HasStdExtZkne, HasStdExtZknh,
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HasStdExtZksed, HasStdExtZksh, HasStdExtZkr,

llvm/test/tools/llvm-mca/RISCV/SiFiveP400/div.s

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -328,12 +328,12 @@ vfsqrt.v v8, v16
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# CHECK: Iterations: 1
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# CHECK-NEXT: Instructions: 320
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# CHECK-NEXT: Total Cycles: 22358
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# CHECK-NEXT: Total Cycles: 19388
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# CHECK-NEXT: Total uOps: 320
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# CHECK: Dispatch Width: 3
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# CHECK-NEXT: uOps Per Cycle: 0.01
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# CHECK-NEXT: IPC: 0.01
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# CHECK-NEXT: uOps Per Cycle: 0.02
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# CHECK-NEXT: IPC: 0.02
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# CHECK-NEXT: Block RThroughput: 14361.0
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# CHECK: Instruction Info:

llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vlseg-vsseg.s

Lines changed: 1 addition & 1 deletion
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@@ -1606,7 +1606,7 @@ vsoxseg8ei64.v v8, (a0), v16
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# CHECK: Iterations: 1
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# CHECK-NEXT: Instructions: 1540
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# CHECK-NEXT: Total Cycles: 29967
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# CHECK-NEXT: Total Cycles: 28335
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# CHECK-NEXT: Total uOps: 1540
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# CHECK: Dispatch Width: 3

llvm/test/tools/llvm-mca/RISCV/SiFiveP600/div.s

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -328,7 +328,7 @@ vfsqrt.v v8, v16
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# CHECK: Iterations: 1
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# CHECK-NEXT: Instructions: 320
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# CHECK-NEXT: Total Cycles: 14613
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# CHECK-NEXT: Total Cycles: 14397
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# CHECK-NEXT: Total uOps: 320
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# CHECK: Dispatch Width: 4

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