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[RISCV][MC] Split tests for A into Zaamo and Zalrsc parts
So that we don't duplicate tests in later patch. Reviewers: topperc, dtcxzyw, asb Reviewed By: asb Pull Request: #79111
1 parent 63f742c commit 9324872

8 files changed

+92
-71
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‎llvm/test/MC/RISCV/rv32a-invalid.s renamed to ‎llvm/test/MC/RISCV/rv32zaamo-invalid.s

Lines changed: 0 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -4,15 +4,8 @@
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amoswap.w a1, a2, a3 # CHECK: :[[@LINE]]:19: error: expected '(' or optional integer offset
55
amomin.w a1, a2, 1 # CHECK: :[[@LINE]]:20: error: expected '(' after optional integer offset
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amomin.w a1, a2, 1(a3) # CHECK: :[[@LINE]]:18: error: optional integer offset must be 0
7-
lr.w a4, a5 # CHECK: :[[@LINE]]:10: error: expected '(' or optional integer offset
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# Only .aq, .rl, and .aqrl suffixes are valid
109
amoxor.w.rlqa a2, a3, (a4) # CHECK: :[[@LINE]]:1: error: unrecognized instruction mnemonic
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amoor.w.aq.rl a4, a5, (a6) # CHECK: :[[@LINE]]:1: error: unrecognized instruction mnemonic
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amoor.w. a4, a5, (a6) # CHECK: :[[@LINE]]:1: error: unrecognized instruction mnemonic
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# lr only takes two operands
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lr.w s0, (s1), s2 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction
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# Note: errors for use of RV64A instructions for RV32 are checked in
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# rv64a-valid.s

‎llvm/test/MC/RISCV/rv32a-valid.s renamed to ‎llvm/test/MC/RISCV/rv32zaamo-valid.s

Lines changed: 0 additions & 26 deletions
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@@ -9,32 +9,6 @@
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# RUN: | llvm-objdump --mattr=+a -M no-aliases -d -r - \
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# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
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# CHECK-ASM-AND-OBJ: lr.w t0, (t1)
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# CHECK-ASM: encoding: [0xaf,0x22,0x03,0x10]
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lr.w t0, (t1)
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# CHECK-ASM-AND-OBJ: lr.w.aq t1, (t2)
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# CHECK-ASM: encoding: [0x2f,0xa3,0x03,0x14]
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lr.w.aq t1, (t2)
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# CHECK-ASM-AND-OBJ: lr.w.rl t2, (t3)
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# CHECK-ASM: encoding: [0xaf,0x23,0x0e,0x12]
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lr.w.rl t2, (t3)
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# CHECK-ASM-AND-OBJ: lr.w.aqrl t3, (t4)
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# CHECK-ASM: encoding: [0x2f,0xae,0x0e,0x16]
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lr.w.aqrl t3, (t4)
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# CHECK-ASM-AND-OBJ: sc.w t6, t5, (t4)
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# CHECK-ASM: encoding: [0xaf,0xaf,0xee,0x19]
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sc.w t6, t5, (t4)
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# CHECK-ASM-AND-OBJ: sc.w.aq t5, t4, (t3)
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# CHECK-ASM: encoding: [0x2f,0x2f,0xde,0x1d]
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sc.w.aq t5, t4, (t3)
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# CHECK-ASM-AND-OBJ: sc.w.rl t4, t3, (t2)
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# CHECK-ASM: encoding: [0xaf,0xae,0xc3,0x1b]
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sc.w.rl t4, t3, (t2)
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# CHECK-ASM-AND-OBJ: sc.w.aqrl t3, t2, (t1)
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# CHECK-ASM: encoding: [0x2f,0x2e,0x73,0x1e]
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sc.w.aqrl t3, t2, (t1)
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# CHECK-ASM-AND-OBJ: amoswap.w a4, ra, (s0)
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# CHECK-ASM: encoding: [0x2f,0x27,0x14,0x08]
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amoswap.w a4, ra, (s0)

‎llvm/test/MC/RISCV/rv32zalrsc-invalid.s

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# RUN: not llvm-mc -triple riscv32 -mattr=+a < %s 2>&1 | FileCheck %s
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# Final operand must have parentheses
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lr.w a4, a5 # CHECK: :[[@LINE]]:10: error: expected '(' or optional integer offset
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# lr only takes two operands
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lr.w s0, (s1), s2 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction

‎llvm/test/MC/RISCV/rv32zalrsc-valid.s

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# RUN: llvm-mc %s -triple=riscv32 -mattr=+a -riscv-no-aliases -show-encoding \
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# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
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# RUN: llvm-mc %s -triple=riscv64 -mattr=+a -riscv-no-aliases -show-encoding \
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# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
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# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+a < %s \
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# RUN: | llvm-objdump --mattr=+a -M no-aliases -d -r - \
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# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
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# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+a < %s \
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# RUN: | llvm-objdump --mattr=+a -M no-aliases -d -r - \
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# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
11+
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# CHECK-ASM-AND-OBJ: lr.w t0, (t1)
13+
# CHECK-ASM: encoding: [0xaf,0x22,0x03,0x10]
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lr.w t0, (t1)
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# CHECK-ASM-AND-OBJ: lr.w.aq t1, (t2)
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# CHECK-ASM: encoding: [0x2f,0xa3,0x03,0x14]
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lr.w.aq t1, (t2)
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# CHECK-ASM-AND-OBJ: lr.w.rl t2, (t3)
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# CHECK-ASM: encoding: [0xaf,0x23,0x0e,0x12]
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lr.w.rl t2, (t3)
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# CHECK-ASM-AND-OBJ: lr.w.aqrl t3, (t4)
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# CHECK-ASM: encoding: [0x2f,0xae,0x0e,0x16]
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lr.w.aqrl t3, (t4)
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# CHECK-ASM-AND-OBJ: sc.w t6, t5, (t4)
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# CHECK-ASM: encoding: [0xaf,0xaf,0xee,0x19]
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sc.w t6, t5, (t4)
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# CHECK-ASM-AND-OBJ: sc.w.aq t5, t4, (t3)
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# CHECK-ASM: encoding: [0x2f,0x2f,0xde,0x1d]
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sc.w.aq t5, t4, (t3)
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# CHECK-ASM-AND-OBJ: sc.w.rl t4, t3, (t2)
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# CHECK-ASM: encoding: [0xaf,0xae,0xc3,0x1b]
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sc.w.rl t4, t3, (t2)
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# CHECK-ASM-AND-OBJ: sc.w.aqrl t3, t2, (t1)
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# CHECK-ASM: encoding: [0x2f,0x2e,0x73,0x1e]
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sc.w.aqrl t3, t2, (t1)

‎llvm/test/MC/RISCV/rv64a-invalid.s renamed to ‎llvm/test/MC/RISCV/rv64zaamo-invalid.s

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -4,12 +4,8 @@
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amoswap.d a1, a2, a3 # CHECK: :[[@LINE]]:19: error: expected '(' or optional integer offset
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amomin.d a1, a2, 1 # CHECK: :[[@LINE]]:20: error: expected '(' after optional integer offset
66
amomin.d a1, a2, 1(a3) # CHECK: :[[@LINE]]:18: error: optional integer offset must be 0
7-
lr.d a4, a5 # CHECK: :[[@LINE]]:10: error: expected '(' or optional integer offset
87

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# Only .aq, .rl, and .aqrl suffixes are valid
109
amoxor.d.rlqa a2, a3, (a4) # CHECK: :[[@LINE]]:1: error: unrecognized instruction mnemonic
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amoor.d.aq.rl a4, a5, (a6) # CHECK: :[[@LINE]]:1: error: unrecognized instruction mnemonic
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amoor.d. a4, a5, (a6) # CHECK: :[[@LINE]]:1: error: unrecognized instruction mnemonic
13-
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# lr only takes two operands
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lr.d s0, (s1), s2 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction

‎llvm/test/MC/RISCV/rv64a-valid.s renamed to ‎llvm/test/MC/RISCV/rv64zaamo-valid.s

Lines changed: 0 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -7,40 +7,6 @@
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# RUN: not llvm-mc -triple riscv32 -mattr=+a < %s 2>&1 \
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# RUN: | FileCheck -check-prefix=CHECK-RV32 %s
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10-
# CHECK-ASM-AND-OBJ: lr.d t0, (t1)
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# CHECK-ASM: encoding: [0xaf,0x32,0x03,0x10]
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# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
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lr.d t0, (t1)
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# CHECK-ASM-AND-OBJ: lr.d.aq t1, (t2)
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# CHECK-ASM: encoding: [0x2f,0xb3,0x03,0x14]
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# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
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lr.d.aq t1, (t2)
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# CHECK-ASM-AND-OBJ: lr.d.rl t2, (t3)
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# CHECK-ASM: encoding: [0xaf,0x33,0x0e,0x12]
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# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
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lr.d.rl t2, (t3)
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# CHECK-ASM-AND-OBJ: lr.d.aqrl t3, (t4)
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# CHECK-ASM: encoding: [0x2f,0xbe,0x0e,0x16]
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# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
25-
lr.d.aqrl t3, (t4)
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# CHECK-ASM-AND-OBJ: sc.d t6, t5, (t4)
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# CHECK-ASM: encoding: [0xaf,0xbf,0xee,0x19]
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# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
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sc.d t6, t5, (t4)
31-
# CHECK-ASM-AND-OBJ: sc.d.aq t5, t4, (t3)
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# CHECK-ASM: encoding: [0x2f,0x3f,0xde,0x1d]
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# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
34-
sc.d.aq t5, t4, (t3)
35-
# CHECK-ASM-AND-OBJ: sc.d.rl t4, t3, (t2)
36-
# CHECK-ASM: encoding: [0xaf,0xbe,0xc3,0x1b]
37-
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
38-
sc.d.rl t4, t3, (t2)
39-
# CHECK-ASM-AND-OBJ: sc.d.aqrl t3, t2, (t1)
40-
# CHECK-ASM: encoding: [0x2f,0x3e,0x73,0x1e]
41-
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
42-
sc.d.aqrl t3, t2, (t1)
43-
4410
# CHECK-ASM-AND-OBJ: amoswap.d a4, ra, (s0)
4511
# CHECK-ASM: encoding: [0x2f,0x37,0x14,0x08]
4612
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}

‎llvm/test/MC/RISCV/rv64zalrsc-invalid.s

Lines changed: 7 additions & 0 deletions
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# RUN: not llvm-mc -triple riscv64 -mattr=+a < %s 2>&1 | FileCheck %s
2+
3+
# Final operand must have parentheses
4+
lr.d a4, a5 # CHECK: :[[@LINE]]:10: error: expected '(' or optional integer offset
5+
6+
# lr only takes two operands
7+
lr.d s0, (s1), s2 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction

‎llvm/test/MC/RISCV/rv64zalrsc-valid.s

Lines changed: 42 additions & 0 deletions
Original file line numberDiff line numberDiff line change
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# RUN: llvm-mc %s -triple=riscv64 -mattr=+a -riscv-no-aliases -show-encoding \
2+
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
3+
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+a < %s \
4+
# RUN: | llvm-objdump --mattr=+a -M no-aliases -d -r - \
5+
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
6+
#
7+
# RUN: not llvm-mc -triple riscv32 -mattr=+a < %s 2>&1 \
8+
# RUN: | FileCheck -check-prefix=CHECK-RV32 %s
9+
10+
# CHECK-ASM-AND-OBJ: lr.d t0, (t1)
11+
# CHECK-ASM: encoding: [0xaf,0x32,0x03,0x10]
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# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
13+
lr.d t0, (t1)
14+
# CHECK-ASM-AND-OBJ: lr.d.aq t1, (t2)
15+
# CHECK-ASM: encoding: [0x2f,0xb3,0x03,0x14]
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# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
17+
lr.d.aq t1, (t2)
18+
# CHECK-ASM-AND-OBJ: lr.d.rl t2, (t3)
19+
# CHECK-ASM: encoding: [0xaf,0x33,0x0e,0x12]
20+
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
21+
lr.d.rl t2, (t3)
22+
# CHECK-ASM-AND-OBJ: lr.d.aqrl t3, (t4)
23+
# CHECK-ASM: encoding: [0x2f,0xbe,0x0e,0x16]
24+
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
25+
lr.d.aqrl t3, (t4)
26+
27+
# CHECK-ASM-AND-OBJ: sc.d t6, t5, (t4)
28+
# CHECK-ASM: encoding: [0xaf,0xbf,0xee,0x19]
29+
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
30+
sc.d t6, t5, (t4)
31+
# CHECK-ASM-AND-OBJ: sc.d.aq t5, t4, (t3)
32+
# CHECK-ASM: encoding: [0x2f,0x3f,0xde,0x1d]
33+
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
34+
sc.d.aq t5, t4, (t3)
35+
# CHECK-ASM-AND-OBJ: sc.d.rl t4, t3, (t2)
36+
# CHECK-ASM: encoding: [0xaf,0xbe,0xc3,0x1b]
37+
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
38+
sc.d.rl t4, t3, (t2)
39+
# CHECK-ASM-AND-OBJ: sc.d.aqrl t3, t2, (t1)
40+
# CHECK-ASM: encoding: [0x2f,0x3e,0x73,0x1e]
41+
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
42+
sc.d.aqrl t3, t2, (t1)

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