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[AArch64] Expand v8i8 cttz (PR39729)
Fix for https://bugs.llvm.org/show_bug.cgi?id=39729. Rather than adding just a case for v8i8 I'm setting cttz to expand for all vector types. Differential Revision: https://reviews.llvm.org/D58008 llvm-svn: 353872
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2 files changed

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‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

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Original file line numberDiff line numberDiff line change
@@ -681,15 +681,6 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::CTLZ, MVT::v1i64, Expand);
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setOperationAction(ISD::CTLZ, MVT::v2i64, Expand);
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setOperationAction(ISD::CTTZ, MVT::v2i8, Expand);
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setOperationAction(ISD::CTTZ, MVT::v4i16, Expand);
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setOperationAction(ISD::CTTZ, MVT::v2i32, Expand);
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setOperationAction(ISD::CTTZ, MVT::v1i64, Expand);
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setOperationAction(ISD::CTTZ, MVT::v16i8, Expand);
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setOperationAction(ISD::CTTZ, MVT::v8i16, Expand);
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setOperationAction(ISD::CTTZ, MVT::v4i32, Expand);
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setOperationAction(ISD::CTTZ, MVT::v2i64, Expand);
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// AArch64 doesn't have MUL.2d:
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setOperationAction(ISD::MUL, MVT::v2i64, Expand);
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// Custom handling for some quad-vector types to detect MULL.
@@ -728,6 +719,7 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::UMUL_LOHI, VT, Expand);
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setOperationAction(ISD::BSWAP, VT, Expand);
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setOperationAction(ISD::CTTZ, VT, Expand);
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for (MVT InnerVT : MVT::vector_valuetypes()) {
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setTruncStoreAction(VT, InnerVT, Expand);

‎llvm/test/CodeGen/AArch64/vec_cttz.ll

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,124 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK
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declare <8 x i8> @llvm.cttz.v8i8(<8 x i8>, i1)
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declare <4 x i16> @llvm.cttz.v4i16(<4 x i16>, i1)
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declare <2 x i32> @llvm.cttz.v2i32(<2 x i32>, i1)
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declare <1 x i64> @llvm.cttz.v1i64(<1 x i64>, i1)
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declare <16 x i8> @llvm.cttz.v16i8(<16 x i8>, i1)
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declare <8 x i16> @llvm.cttz.v8i16(<8 x i16>, i1)
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declare <4 x i32> @llvm.cttz.v4i32(<4 x i32>, i1)
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declare <2 x i64> @llvm.cttz.v2i64(<2 x i64>, i1)
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define <8 x i8> @cttz_v8i8(<8 x i8> %a) nounwind {
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; CHECK-LABEL: cttz_v8i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi v1.8b, #1
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; CHECK-NEXT: sub v1.8b, v0.8b, v1.8b
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; CHECK-NEXT: bic v0.8b, v1.8b, v0.8b
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; CHECK-NEXT: cnt v0.8b, v0.8b
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; CHECK-NEXT: ret
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%b = call <8 x i8> @llvm.cttz.v8i8(<8 x i8> %a, i1 true)
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ret <8 x i8> %b
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}
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define <4 x i16> @cttz_v4i16(<4 x i16> %a) nounwind {
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; CHECK-LABEL: cttz_v4i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi v1.4h, #1
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; CHECK-NEXT: sub v1.4h, v0.4h, v1.4h
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; CHECK-NEXT: bic v0.8b, v1.8b, v0.8b
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; CHECK-NEXT: clz v0.4h, v0.4h
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; CHECK-NEXT: movi v1.4h, #16
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; CHECK-NEXT: sub v0.4h, v1.4h, v0.4h
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; CHECK-NEXT: ret
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%b = call <4 x i16> @llvm.cttz.v4i16(<4 x i16> %a, i1 true)
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ret <4 x i16> %b
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}
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define <2 x i32> @cttz_v2i32(<2 x i32> %a) nounwind {
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; CHECK-LABEL: cttz_v2i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi v1.2s, #1
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; CHECK-NEXT: sub v1.2s, v0.2s, v1.2s
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; CHECK-NEXT: bic v0.8b, v1.8b, v0.8b
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; CHECK-NEXT: clz v0.2s, v0.2s
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; CHECK-NEXT: movi v1.2s, #32
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; CHECK-NEXT: sub v0.2s, v1.2s, v0.2s
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; CHECK-NEXT: ret
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%b = call <2 x i32> @llvm.cttz.v2i32(<2 x i32> %a, i1 true)
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ret <2 x i32> %b
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}
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define <1 x i64> @cttz_v1i64(<1 x i64> %a) nounwind {
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; CHECK-LABEL: cttz_v1i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: orr w8, wzr, #0x1
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; CHECK-NEXT: fmov d1, x8
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; CHECK-NEXT: sub d1, d0, d1
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; CHECK-NEXT: bic v0.8b, v1.8b, v0.8b
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; CHECK-NEXT: cnt v0.8b, v0.8b
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; CHECK-NEXT: uaddlp v0.4h, v0.8b
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; CHECK-NEXT: uaddlp v0.2s, v0.4h
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; CHECK-NEXT: uaddlp v0.1d, v0.2s
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; CHECK-NEXT: ret
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%b = call <1 x i64> @llvm.cttz.v1i64(<1 x i64> %a, i1 true)
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ret <1 x i64> %b
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}
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define <16 x i8> @cttz_v16i8(<16 x i8> %a) nounwind {
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; CHECK-LABEL: cttz_v16i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi v1.16b, #1
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; CHECK-NEXT: sub v1.16b, v0.16b, v1.16b
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; CHECK-NEXT: bic v0.16b, v1.16b, v0.16b
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; CHECK-NEXT: cnt v0.16b, v0.16b
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; CHECK-NEXT: ret
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%b = call <16 x i8> @llvm.cttz.v16i8(<16 x i8> %a, i1 true)
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ret <16 x i8> %b
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}
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define <8 x i16> @cttz_v8i16(<8 x i16> %a) nounwind {
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; CHECK-LABEL: cttz_v8i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi v1.8h, #1
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; CHECK-NEXT: sub v1.8h, v0.8h, v1.8h
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; CHECK-NEXT: bic v0.16b, v1.16b, v0.16b
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; CHECK-NEXT: clz v0.8h, v0.8h
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; CHECK-NEXT: movi v1.8h, #16
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; CHECK-NEXT: sub v0.8h, v1.8h, v0.8h
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; CHECK-NEXT: ret
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%b = call <8 x i16> @llvm.cttz.v8i16(<8 x i16> %a, i1 true)
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ret <8 x i16> %b
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}
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define <4 x i32> @cttz_v4i32(<4 x i32> %a) nounwind {
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; CHECK-LABEL: cttz_v4i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi v1.4s, #1
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; CHECK-NEXT: sub v1.4s, v0.4s, v1.4s
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; CHECK-NEXT: bic v0.16b, v1.16b, v0.16b
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; CHECK-NEXT: clz v0.4s, v0.4s
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; CHECK-NEXT: movi v1.4s, #32
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; CHECK-NEXT: sub v0.4s, v1.4s, v0.4s
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; CHECK-NEXT: ret
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%b = call <4 x i32> @llvm.cttz.v4i32(<4 x i32> %a, i1 true)
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ret <4 x i32> %b
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}
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define <2 x i64> @cttz_v2i64(<2 x i64> %a) nounwind {
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; CHECK-LABEL: cttz_v2i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: orr w8, wzr, #0x1
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; CHECK-NEXT: dup v1.2d, x8
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; CHECK-NEXT: sub v1.2d, v0.2d, v1.2d
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; CHECK-NEXT: bic v0.16b, v1.16b, v0.16b
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; CHECK-NEXT: cnt v0.16b, v0.16b
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; CHECK-NEXT: uaddlp v0.8h, v0.16b
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; CHECK-NEXT: uaddlp v0.4s, v0.8h
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; CHECK-NEXT: uaddlp v0.2d, v0.4s
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; CHECK-NEXT: ret
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%b = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> %a, i1 true)
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ret <2 x i64> %b
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}

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