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AMDGPU: Set max supported div/rem size to 64 (#80669)
This enables IR expansion for i128 divisions. The vector case is still broken because ExpandLargeDivRem doesn't try to handle them. Fixes: SWDEV-426193
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llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

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@@ -577,6 +577,7 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,
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ISD::AssertSext, ISD::INTRINSIC_WO_CHAIN});
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setMaxAtomicSizeInBitsSupported(64);
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setMaxDivRemBitWidthSupported(64);
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}
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bool AMDGPUTargetLowering::mayIgnoreSignedZero(SDValue Op) const {

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