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[WebAssembly][SIMD] Rename shuffle, swizzle, and load_splats
These instructions previously used prefixes like v8x16 to signify that they were agnostic between float and int interpretations. We renamed these instructions to remove this form of prefix in WebAssembly/simd#297 and WebAssembly/simd#316 and this commit brings the names in LLVM up to date. Differential Revision: https://reviews.llvm.org/D93722
1 parent f7a2612 commit a781a70

13 files changed

+142
-142
lines changed

‎llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -194,7 +194,7 @@ inline unsigned GetDefaultP2AlignAny(unsigned Opc) {
194194
WASM_LOAD_STORE(ATOMIC_RMW8_U_XCHG_I64)
195195
WASM_LOAD_STORE(ATOMIC_RMW8_U_CMPXCHG_I32)
196196
WASM_LOAD_STORE(ATOMIC_RMW8_U_CMPXCHG_I64)
197-
WASM_LOAD_STORE(LOAD_SPLAT_v8x16)
197+
WASM_LOAD_STORE(LOAD8_SPLAT)
198198
WASM_LOAD_STORE(LOAD_LANE_v16i8)
199199
WASM_LOAD_STORE(STORE_LANE_v16i8)
200200
return 0;
@@ -222,7 +222,7 @@ inline unsigned GetDefaultP2AlignAny(unsigned Opc) {
222222
WASM_LOAD_STORE(ATOMIC_RMW16_U_XCHG_I64)
223223
WASM_LOAD_STORE(ATOMIC_RMW16_U_CMPXCHG_I32)
224224
WASM_LOAD_STORE(ATOMIC_RMW16_U_CMPXCHG_I64)
225-
WASM_LOAD_STORE(LOAD_SPLAT_v16x8)
225+
WASM_LOAD_STORE(LOAD16_SPLAT)
226226
WASM_LOAD_STORE(LOAD_LANE_v8i16)
227227
WASM_LOAD_STORE(STORE_LANE_v8i16)
228228
return 1;
@@ -253,7 +253,7 @@ inline unsigned GetDefaultP2AlignAny(unsigned Opc) {
253253
WASM_LOAD_STORE(ATOMIC_RMW32_U_CMPXCHG_I64)
254254
WASM_LOAD_STORE(MEMORY_ATOMIC_NOTIFY)
255255
WASM_LOAD_STORE(MEMORY_ATOMIC_WAIT32)
256-
WASM_LOAD_STORE(LOAD_SPLAT_v32x4)
256+
WASM_LOAD_STORE(LOAD32_SPLAT)
257257
WASM_LOAD_STORE(LOAD_ZERO_v4i32)
258258
WASM_LOAD_STORE(LOAD_LANE_v4i32)
259259
WASM_LOAD_STORE(STORE_LANE_v4i32)
@@ -272,7 +272,7 @@ inline unsigned GetDefaultP2AlignAny(unsigned Opc) {
272272
WASM_LOAD_STORE(ATOMIC_RMW_XCHG_I64)
273273
WASM_LOAD_STORE(ATOMIC_RMW_CMPXCHG_I64)
274274
WASM_LOAD_STORE(MEMORY_ATOMIC_WAIT64)
275-
WASM_LOAD_STORE(LOAD_SPLAT_v64x2)
275+
WASM_LOAD_STORE(LOAD64_SPLAT)
276276
WASM_LOAD_STORE(LOAD_EXTEND_S_v8i16)
277277
WASM_LOAD_STORE(LOAD_EXTEND_U_v8i16)
278278
WASM_LOAD_STORE(LOAD_EXTEND_S_v4i32)

‎llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

Lines changed: 23 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -64,55 +64,55 @@ defm : LoadPatOffsetOnly<vec_t, load, "LOAD_V128">;
6464
defm : LoadPatGlobalAddrOffOnly<vec_t, load, "LOAD_V128">;
6565
}
6666

67-
// vNxM.load_splat
68-
multiclass SIMDLoadSplat<string vec, bits<32> simdop> {
67+
// v128.loadX_splat
68+
multiclass SIMDLoadSplat<int size, bits<32> simdop> {
6969
let mayLoad = 1, UseNamedOperandTable = 1 in {
70-
defm LOAD_SPLAT_#vec#_A32 :
70+
defm LOAD#size#_SPLAT_A32 :
7171
SIMD_I<(outs V128:$dst),
7272
(ins P2Align:$p2align, offset32_op:$off, I32:$addr),
7373
(outs),
7474
(ins P2Align:$p2align, offset32_op:$off), [],
75-
vec#".load_splat\t$dst, ${off}(${addr})$p2align",
76-
vec#".load_splat\t$off$p2align", simdop>;
77-
defm LOAD_SPLAT_#vec#_A64 :
75+
"v128.load"#size#"_splat\t$dst, ${off}(${addr})$p2align",
76+
"v128.load"#size#"_splat\t$off$p2align", simdop>;
77+
defm LOAD#size#_SPLAT_A64 :
7878
SIMD_I<(outs V128:$dst),
7979
(ins P2Align:$p2align, offset64_op:$off, I64:$addr),
8080
(outs),
8181
(ins P2Align:$p2align, offset64_op:$off), [],
82-
vec#".load_splat\t$dst, ${off}(${addr})$p2align",
83-
vec#".load_splat\t$off$p2align", simdop>;
82+
"v128.load"#size#"_splat\t$dst, ${off}(${addr})$p2align",
83+
"v128.load"#size#"_splat\t$off$p2align", simdop>;
8484
}
8585
}
8686

87-
defm "" : SIMDLoadSplat<"v8x16", 7>;
88-
defm "" : SIMDLoadSplat<"v16x8", 8>;
89-
defm "" : SIMDLoadSplat<"v32x4", 9>;
90-
defm "" : SIMDLoadSplat<"v64x2", 10>;
87+
defm "" : SIMDLoadSplat<8, 7>;
88+
defm "" : SIMDLoadSplat<16, 8>;
89+
defm "" : SIMDLoadSplat<32, 9>;
90+
defm "" : SIMDLoadSplat<64, 10>;
9191

9292
def wasm_load_splat_t : SDTypeProfile<1, 1, [SDTCisPtrTy<1>]>;
9393
def wasm_load_splat : SDNode<"WebAssemblyISD::LOAD_SPLAT", wasm_load_splat_t,
9494
[SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
9595
def load_splat : PatFrag<(ops node:$addr), (wasm_load_splat node:$addr)>;
9696

97-
foreach args = [["v16i8", "v8x16"], ["v8i16", "v16x8"], ["v4i32", "v32x4"],
98-
["v2i64", "v64x2"], ["v4f32", "v32x4"], ["v2f64", "v64x2"]] in {
97+
foreach args = [["v16i8", "8"], ["v8i16", "16"], ["v4i32", "32"],
98+
["v2i64", "64"], ["v4f32", "32"], ["v2f64", "64"]] in {
9999
defm : LoadPatNoOffset<!cast<ValueType>(args[0]),
100100
load_splat,
101-
"LOAD_SPLAT_"#args[1]>;
101+
"LOAD"#args[1]#"_SPLAT">;
102102
defm : LoadPatImmOff<!cast<ValueType>(args[0]),
103103
load_splat,
104104
regPlusImm,
105-
"LOAD_SPLAT_"#args[1]>;
105+
"LOAD"#args[1]#"_SPLAT">;
106106
defm : LoadPatImmOff<!cast<ValueType>(args[0]),
107107
load_splat,
108108
or_is_add,
109-
"LOAD_SPLAT_"#args[1]>;
109+
"LOAD"#args[1]#"_SPLAT">;
110110
defm : LoadPatOffsetOnly<!cast<ValueType>(args[0]),
111111
load_splat,
112-
"LOAD_SPLAT_"#args[1]>;
112+
"LOAD"#args[1]#"_SPLAT">;
113113
defm : LoadPatGlobalAddrOffOnly<!cast<ValueType>(args[0]),
114114
load_splat,
115-
"LOAD_SPLAT_"#args[1]>;
115+
"LOAD"#args[1]#"_SPLAT">;
116116
}
117117

118118
// Load and extend
@@ -401,10 +401,10 @@ defm SHUFFLE :
401401
vec_i8imm_op:$mC, vec_i8imm_op:$mD,
402402
vec_i8imm_op:$mE, vec_i8imm_op:$mF),
403403
[],
404-
"v8x16.shuffle\t$dst, $x, $y, "#
404+
"i8x16.shuffle\t$dst, $x, $y, "#
405405
"$m0, $m1, $m2, $m3, $m4, $m5, $m6, $m7, "#
406406
"$m8, $m9, $mA, $mB, $mC, $mD, $mE, $mF",
407-
"v8x16.shuffle\t"#
407+
"i8x16.shuffle\t"#
408408
"$m0, $m1, $m2, $m3, $m4, $m5, $m6, $m7, "#
409409
"$m8, $m9, $mA, $mB, $mC, $mD, $mE, $mF",
410410
13>;
@@ -433,14 +433,14 @@ def : Pat<(vec_t (wasm_shuffle (vec_t V128:$x), (vec_t V128:$y),
433433
(i32 LaneIdx32:$mE), (i32 LaneIdx32:$mF)))>;
434434
}
435435

436-
// Swizzle lanes: v8x16.swizzle
436+
// Swizzle lanes: i8x16.swizzle
437437
def wasm_swizzle_t : SDTypeProfile<1, 2, []>;
438438
def wasm_swizzle : SDNode<"WebAssemblyISD::SWIZZLE", wasm_swizzle_t>;
439439
defm SWIZZLE :
440440
SIMD_I<(outs V128:$dst), (ins V128:$src, V128:$mask), (outs), (ins),
441441
[(set (v16i8 V128:$dst),
442442
(wasm_swizzle (v16i8 V128:$src), (v16i8 V128:$mask)))],
443-
"v8x16.swizzle\t$dst, $src, $mask", "v8x16.swizzle", 14>;
443+
"i8x16.swizzle\t$dst, $src, $mask", "i8x16.swizzle", 14>;
444444

445445
def : Pat<(int_wasm_swizzle (v16i8 V128:$src), (v16i8 V128:$mask)),
446446
(SWIZZLE V128:$src, V128:$mask)>;

‎llvm/test/CodeGen/WebAssembly/simd-build-vector.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -178,7 +178,7 @@ define <8 x i16> @splat_common_arg_i16x8(i16 %a, i16 %b, i16 %c) {
178178

179179
; CHECK-LABEL: swizzle_one_i8x16:
180180
; CHECK-NEXT: .functype swizzle_one_i8x16 (v128, v128) -> (v128)
181-
; CHECK-NEXT: v8x16.swizzle $push[[L0:[0-9]+]]=, $0, $1
181+
; CHECK-NEXT: i8x16.swizzle $push[[L0:[0-9]+]]=, $0, $1
182182
; CHECK-NEXT: return $pop[[L0]]
183183
define <16 x i8> @swizzle_one_i8x16(<16 x i8> %src, <16 x i8> %mask) {
184184
%m0 = extractelement <16 x i8> %mask, i32 0
@@ -189,7 +189,7 @@ define <16 x i8> @swizzle_one_i8x16(<16 x i8> %src, <16 x i8> %mask) {
189189

190190
; CHECK-LABEL: swizzle_all_i8x16:
191191
; CHECK-NEXT: .functype swizzle_all_i8x16 (v128, v128) -> (v128)
192-
; CHECK-NEXT: v8x16.swizzle $push[[L0:[0-9]+]]=, $0, $1
192+
; CHECK-NEXT: i8x16.swizzle $push[[L0:[0-9]+]]=, $0, $1
193193
; CHECK-NEXT: return $pop[[L0]]
194194
define <16 x i8> @swizzle_all_i8x16(<16 x i8> %src, <16 x i8> %mask) {
195195
%m0 = extractelement <16 x i8> %mask, i32 0
@@ -256,7 +256,7 @@ define <8 x i16> @swizzle_one_i16x8(<8 x i16> %src, <8 x i16> %mask) {
256256

257257
; CHECK-LABEL: mashup_swizzle_i8x16:
258258
; CHECK-NEXT: .functype mashup_swizzle_i8x16 (v128, v128, i32) -> (v128)
259-
; CHECK-NEXT: v8x16.swizzle $push[[L0:[0-9]+]]=, $0, $1
259+
; CHECK-NEXT: i8x16.swizzle $push[[L0:[0-9]+]]=, $0, $1
260260
; CHECK: i8x16.replace_lane
261261
; CHECK: i8x16.replace_lane
262262
; CHECK: i8x16.replace_lane

‎llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,7 @@ target triple = "wasm32-unknown-unknown"
1313
; ==============================================================================
1414
; CHECK-LABEL: swizzle_v16i8:
1515
; SIMD128-NEXT: .functype swizzle_v16i8 (v128, v128) -> (v128){{$}}
16-
; SIMD128-NEXT: v8x16.swizzle $push[[R:[0-9]+]]=, $0, $1{{$}}
16+
; SIMD128-NEXT: i8x16.swizzle $push[[R:[0-9]+]]=, $0, $1{{$}}
1717
; SIMD128-NEXT: return $pop[[R]]{{$}}
1818
declare <16 x i8> @llvm.wasm.swizzle(<16 x i8>, <16 x i8>)
1919
define <16 x i8> @swizzle_v16i8(<16 x i8> %x, <16 x i8> %y) {
@@ -164,9 +164,9 @@ define <16 x i8> @narrow_unsigned_v16i8(<8 x i16> %low, <8 x i16> %high) {
164164
}
165165

166166
; CHECK-LABEL: shuffle_v16i8:
167-
; NO-SIMD128-NOT: v8x16
167+
; NO-SIMD128-NOT: i8x16
168168
; SIMD128-NEXT: .functype shuffle_v16i8 (v128, v128) -> (v128){{$}}
169-
; SIMD128-NEXT: v8x16.shuffle $push[[R:[0-9]+]]=, $0, $1,
169+
; SIMD128-NEXT: i8x16.shuffle $push[[R:[0-9]+]]=, $0, $1,
170170
; SIMD128-SAME: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0{{$}}
171171
; SIMD128-NEXT: return $pop[[R]]{{$}}
172172
declare <16 x i8> @llvm.wasm.shuffle(
@@ -180,9 +180,9 @@ define <16 x i8> @shuffle_v16i8(<16 x i8> %x, <16 x i8> %y) {
180180
}
181181

182182
; CHECK-LABEL: shuffle_undef_v16i8:
183-
; NO-SIMD128-NOT: v8x16
183+
; NO-SIMD128-NOT: i8x16
184184
; SIMD128-NEXT: .functype shuffle_undef_v16i8 (v128, v128) -> (v128){{$}}
185-
; SIMD128-NEXT: v8x16.shuffle $push[[R:[0-9]+]]=, $0, $1,
185+
; SIMD128-NEXT: i8x16.shuffle $push[[R:[0-9]+]]=, $0, $1,
186186
; SIMD128-SAME: 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2{{$}}
187187
; SIMD128-NEXT: return $pop[[R]]{{$}}
188188
define <16 x i8> @shuffle_undef_v16i8(<16 x i8> %x, <16 x i8> %y) {

‎llvm/test/CodeGen/WebAssembly/simd-load-splat.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@ target triple = "wasm32-unknown-unknown"
99
; CHECK-LABEL: load_splat:
1010
; CHECK-NEXT: .functype load_splat (i32, i32) -> (i32)
1111
; CHECK-NEXT: i32.load8_u $[[E:[0-9]+]]=, 0($0){{$}}
12-
; CHECK-NEXT: v8x16.load_splat $push[[V:[0-9]+]]=, 0($0){{$}}
12+
; CHECK-NEXT: v128.load8_splat $push[[V:[0-9]+]]=, 0($0){{$}}
1313
; CHECK-NEXT: v128.store 0($1), $pop[[V]]{{$}}
1414
; CHECK-NEXT: return $[[E]]{{$}}
1515
define i8 @load_splat(i8* %p, <16 x i8>* %out) {

‎llvm/test/CodeGen/WebAssembly/simd-load-store-alignment.ll

Lines changed: 18 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -89,11 +89,11 @@ define void @store_v16i8_a32(<16 x i8> *%p, <16 x i8> %v) {
8989
ret void
9090
}
9191

92-
; 1 is the default alignment for v8x16.load_splat so no attribute is needed.
92+
; 1 is the default alignment for v128.load8_splat so no attribute is needed.
9393

9494
; CHECK-LABEL: load_splat_v16i8_a1:
9595
; CHECK-NEXT: .functype load_splat_v16i8_a1 (i32) -> (v128){{$}}
96-
; CHECK-NEXT: v8x16.load_splat $push[[R:[0-9]+]]=, 0($0){{$}}
96+
; CHECK-NEXT: v128.load8_splat $push[[R:[0-9]+]]=, 0($0){{$}}
9797
; CHECK-NEXT: return $pop[[R]]{{$}}
9898
define <16 x i8> @load_splat_v16i8_a1(i8* %p) {
9999
%e = load i8, i8* %p, align 1
@@ -106,7 +106,7 @@ define <16 x i8> @load_splat_v16i8_a1(i8* %p) {
106106

107107
; CHECK-LABEL: load_splat_v16i8_a2:
108108
; CHECK-NEXT: .functype load_splat_v16i8_a2 (i32) -> (v128){{$}}
109-
; CHECK-NEXT: v8x16.load_splat $push[[R:[0-9]+]]=, 0($0){{$}}
109+
; CHECK-NEXT: v128.load8_splat $push[[R:[0-9]+]]=, 0($0){{$}}
110110
; CHECK-NEXT: return $pop[[R]]{{$}}
111111
define <16 x i8> @load_splat_v16i8_a2(i8* %p) {
112112
%e = load i8, i8* %p, align 2
@@ -304,7 +304,7 @@ define <8 x i16> @load_sext_v8i16_a16(<8 x i8>* %p) {
304304

305305
; CHECK-LABEL: load_splat_v8i16_a1:
306306
; CHECK-NEXT: .functype load_splat_v8i16_a1 (i32) -> (v128){{$}}
307-
; CHECK-NEXT: v16x8.load_splat $push[[R:[0-9]+]]=, 0($0):p2align=0{{$}}
307+
; CHECK-NEXT: v128.load16_splat $push[[R:[0-9]+]]=, 0($0):p2align=0{{$}}
308308
; CHECK-NEXT: return $pop[[R]]{{$}}
309309
define <8 x i16> @load_splat_v8i16_a1(i16* %p) {
310310
%e = load i16, i16* %p, align 1
@@ -313,11 +313,11 @@ define <8 x i16> @load_splat_v8i16_a1(i16* %p) {
313313
ret <8 x i16> %v2
314314
}
315315

316-
; 2 is the default alignment for v16x8.load_splat so no attribute is needed.
316+
; 2 is the default alignment for v128.load16_splat so no attribute is needed.
317317

318318
; CHECK-LABEL: load_splat_v8i16_a2:
319319
; CHECK-NEXT: .functype load_splat_v8i16_a2 (i32) -> (v128){{$}}
320-
; CHECK-NEXT: v16x8.load_splat $push[[R:[0-9]+]]=, 0($0){{$}}
320+
; CHECK-NEXT: v128.load16_splat $push[[R:[0-9]+]]=, 0($0){{$}}
321321
; CHECK-NEXT: return $pop[[R]]{{$}}
322322
define <8 x i16> @load_splat_v8i16_a2(i16* %p) {
323323
%e = load i16, i16* %p, align 2
@@ -330,7 +330,7 @@ define <8 x i16> @load_splat_v8i16_a2(i16* %p) {
330330

331331
; CHECK-LABEL: load_splat_v8i16_a4:
332332
; CHECK-NEXT: .functype load_splat_v8i16_a4 (i32) -> (v128){{$}}
333-
; CHECK-NEXT: v16x8.load_splat $push[[R:[0-9]+]]=, 0($0){{$}}
333+
; CHECK-NEXT: v128.load16_splat $push[[R:[0-9]+]]=, 0($0){{$}}
334334
; CHECK-NEXT: return $pop[[R]]{{$}}
335335
define <8 x i16> @load_splat_v8i16_a4(i16* %p) {
336336
%e = load i16, i16* %p, align 4
@@ -528,7 +528,7 @@ define <4 x i32> @load_sext_v4i32_a16(<4 x i16>* %p) {
528528

529529
; CHECK-LABEL: load_splat_v4i32_a1:
530530
; CHECK-NEXT: .functype load_splat_v4i32_a1 (i32) -> (v128){{$}}
531-
; CHECK-NEXT: v32x4.load_splat $push[[R:[0-9]+]]=, 0($0):p2align=0{{$}}
531+
; CHECK-NEXT: v128.load32_splat $push[[R:[0-9]+]]=, 0($0):p2align=0{{$}}
532532
; CHECK-NEXT: return $pop[[R]]{{$}}
533533
define <4 x i32> @load_splat_v4i32_a1(i32* %addr) {
534534
%e = load i32, i32* %addr, align 1
@@ -539,7 +539,7 @@ define <4 x i32> @load_splat_v4i32_a1(i32* %addr) {
539539

540540
; CHECK-LABEL: load_splat_v4i32_a2:
541541
; CHECK-NEXT: .functype load_splat_v4i32_a2 (i32) -> (v128){{$}}
542-
; CHECK-NEXT: v32x4.load_splat $push[[R:[0-9]+]]=, 0($0):p2align=1{{$}}
542+
; CHECK-NEXT: v128.load32_splat $push[[R:[0-9]+]]=, 0($0):p2align=1{{$}}
543543
; CHECK-NEXT: return $pop[[R]]{{$}}
544544
define <4 x i32> @load_splat_v4i32_a2(i32* %addr) {
545545
%e = load i32, i32* %addr, align 2
@@ -548,11 +548,11 @@ define <4 x i32> @load_splat_v4i32_a2(i32* %addr) {
548548
ret <4 x i32> %v2
549549
}
550550

551-
; 4 is the default alignment for v32x4.load_splat so no attribute is needed.
551+
; 4 is the default alignment for v128.load32_splat so no attribute is needed.
552552

553553
; CHECK-LABEL: load_splat_v4i32_a4:
554554
; CHECK-NEXT: .functype load_splat_v4i32_a4 (i32) -> (v128){{$}}
555-
; CHECK-NEXT: v32x4.load_splat $push[[R:[0-9]+]]=, 0($0){{$}}
555+
; CHECK-NEXT: v128.load32_splat $push[[R:[0-9]+]]=, 0($0){{$}}
556556
; CHECK-NEXT: return $pop[[R]]{{$}}
557557
define <4 x i32> @load_splat_v4i32_a4(i32* %addr) {
558558
%e = load i32, i32* %addr, align 4
@@ -565,7 +565,7 @@ define <4 x i32> @load_splat_v4i32_a4(i32* %addr) {
565565

566566
; CHECK-LABEL: load_splat_v4i32_a8:
567567
; CHECK-NEXT: .functype load_splat_v4i32_a8 (i32) -> (v128){{$}}
568-
; CHECK-NEXT: v32x4.load_splat $push[[R:[0-9]+]]=, 0($0){{$}}
568+
; CHECK-NEXT: v128.load32_splat $push[[R:[0-9]+]]=, 0($0){{$}}
569569
; CHECK-NEXT: return $pop[[R]]{{$}}
570570
define <4 x i32> @load_splat_v4i32_a8(i32* %addr) {
571571
%e = load i32, i32* %addr, align 8
@@ -660,7 +660,7 @@ define void @store_v2i64_a32(<2 x i64> *%p, <2 x i64> %v) {
660660

661661
; CHECK-LABEL: load_splat_v2i64_a1:
662662
; CHECK-NEXT: .functype load_splat_v2i64_a1 (i32) -> (v128){{$}}
663-
; CHECK-NEXT: v64x2.load_splat $push[[R:[0-9]+]]=, 0($0):p2align=0{{$}}
663+
; CHECK-NEXT: v128.load64_splat $push[[R:[0-9]+]]=, 0($0):p2align=0{{$}}
664664
; CHECK-NEXT: return $pop[[R]]{{$}}
665665
define <2 x i64> @load_splat_v2i64_a1(i64* %p) {
666666
%e = load i64, i64* %p, align 1
@@ -671,7 +671,7 @@ define <2 x i64> @load_splat_v2i64_a1(i64* %p) {
671671

672672
; CHECK-LABEL: load_splat_v2i64_a2:
673673
; CHECK-NEXT: .functype load_splat_v2i64_a2 (i32) -> (v128){{$}}
674-
; CHECK-NEXT: v64x2.load_splat $push[[R:[0-9]+]]=, 0($0):p2align=1{{$}}
674+
; CHECK-NEXT: v128.load64_splat $push[[R:[0-9]+]]=, 0($0):p2align=1{{$}}
675675
; CHECK-NEXT: return $pop[[R]]{{$}}
676676
define <2 x i64> @load_splat_v2i64_a2(i64* %p) {
677677
%e = load i64, i64* %p, align 2
@@ -682,7 +682,7 @@ define <2 x i64> @load_splat_v2i64_a2(i64* %p) {
682682

683683
; CHECK-LABEL: load_splat_v2i64_a4:
684684
; CHECK-NEXT: .functype load_splat_v2i64_a4 (i32) -> (v128){{$}}
685-
; CHECK-NEXT: v64x2.load_splat $push[[R:[0-9]+]]=, 0($0):p2align=2{{$}}
685+
; CHECK-NEXT: v128.load64_splat $push[[R:[0-9]+]]=, 0($0):p2align=2{{$}}
686686
; CHECK-NEXT: return $pop[[R]]{{$}}
687687
define <2 x i64> @load_splat_v2i64_a4(i64* %p) {
688688
%e = load i64, i64* %p, align 4
@@ -691,11 +691,11 @@ define <2 x i64> @load_splat_v2i64_a4(i64* %p) {
691691
ret <2 x i64> %v2
692692
}
693693

694-
; 8 is the default alignment for v64x2.load_splat so no attribute is needed.
694+
; 8 is the default alignment for v128.load64_splat so no attribute is needed.
695695

696696
; CHECK-LABEL: load_splat_v2i64_a8:
697697
; CHECK-NEXT: .functype load_splat_v2i64_a8 (i32) -> (v128){{$}}
698-
; CHECK-NEXT: v64x2.load_splat $push[[R:[0-9]+]]=, 0($0){{$}}
698+
; CHECK-NEXT: v128.load64_splat $push[[R:[0-9]+]]=, 0($0){{$}}
699699
; CHECK-NEXT: return $pop[[R]]{{$}}
700700
define <2 x i64> @load_splat_v2i64_a8(i64* %p) {
701701
%e = load i64, i64* %p, align 8
@@ -708,7 +708,7 @@ define <2 x i64> @load_splat_v2i64_a8(i64* %p) {
708708

709709
; CHECK-LABEL: load_splat_v2i64_a16:
710710
; CHECK-NEXT: .functype load_splat_v2i64_a16 (i32) -> (v128){{$}}
711-
; CHECK-NEXT: v64x2.load_splat $push[[R:[0-9]+]]=, 0($0){{$}}
711+
; CHECK-NEXT: v128.load64_splat $push[[R:[0-9]+]]=, 0($0){{$}}
712712
; CHECK-NEXT: return $pop[[R]]{{$}}
713713
define <2 x i64> @load_splat_v2i64_a16(i64* %p) {
714714
%e = load i64, i64* %p, align 16

‎llvm/test/CodeGen/WebAssembly/simd-nested-shuffles.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,7 @@
66
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
77
target triple = "wasm32-unknown-unknown"
88

9-
; CHECK: v8x16.shuffle
9+
; CHECK: i8x16.shuffle
1010
define <4 x i32> @foo(<4 x i32> %x) {
1111
%1 = shufflevector <4 x i32> %x, <4 x i32> undef,
1212
<4 x i32> <i32 2, i32 3, i32 undef, i32 undef>

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