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[AMDGPU] Remove wavefrontsize feature from GFX10+ (#98400)
Processor definition shall not include a default feature which may be switched off by a different wave size. This allows not to write -mattr=-wavefrontsize32,+wavefrontsize64 in tests.
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+377
-349
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10 files changed

+377
-349
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPU.td

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1464,7 +1464,6 @@ def FeatureISAVersion10_Common : FeatureSet<
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FeatureLDSBankCount32,
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FeatureDLInsts,
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FeatureNSAEncoding,
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FeatureWavefrontSize32,
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FeatureBackOffBarrier]>;
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def FeatureISAVersion10_1_Common : FeatureSet<
@@ -1548,7 +1547,6 @@ def FeatureISAVersion11_Common : FeatureSet<
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FeatureDot10Insts,
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FeatureNSAEncoding,
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FeaturePartialNSAEncoding,
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FeatureWavefrontSize32,
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FeatureShaderCyclesRegister,
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FeatureArchitectedFlatScratch,
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FeatureAtomicFaddRtnInsts,
@@ -1625,7 +1623,6 @@ def FeatureISAVersion12 : FeatureSet<
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FeatureDot11Insts,
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FeatureNSAEncoding,
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FeaturePartialNSAEncoding,
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FeatureWavefrontSize32,
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FeatureShaderCyclesHiLoRegisters,
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FeatureArchitectedFlatScratch,
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FeatureArchitectedSGPRs,

‎llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp

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@@ -105,6 +105,14 @@ GCNSubtarget::initializeSubtargetDependencies(const Triple &TT,
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: AMDGPUSubtarget::SOUTHERN_ISLANDS;
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}
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108+
if (!hasFeature(AMDGPU::FeatureWavefrontSize32) &&
109+
!hasFeature(AMDGPU::FeatureWavefrontSize64)) {
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// If there is no default wave size it must be a generation before gfx10,
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// these have FeatureWavefrontSize64 in their definition already. For gfx10+
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// set wave32 as a default.
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ToggleFeature(AMDGPU::FeatureWavefrontSize32);
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}
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// We don't support FP64 for EG/NI atm.
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assert(!hasFP64() || (getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS));
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‎llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1408,6 +1408,15 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
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copySTI().ToggleFeature("southern-islands");
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}
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FeatureBitset FB = getFeatureBits();
1412+
if (!FB[AMDGPU::FeatureWavefrontSize64] &&
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!FB[AMDGPU::FeatureWavefrontSize32]) {
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// If there is no default wave size it must be a generation before gfx10,
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// these have FeatureWavefrontSize64 in their definition already. For
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// gfx10+ set wave32 as a default.
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copySTI().ToggleFeature(AMDGPU::FeatureWavefrontSize32);
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}
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setAvailableFeatures(ComputeAvailableFeatures(getFeatureBits()));
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AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(getSTI().getCPU());

‎llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp

Lines changed: 18 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -45,10 +45,26 @@ using namespace llvm;
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using DecodeStatus = llvm::MCDisassembler::DecodeStatus;
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48+
static const MCSubtargetInfo &addDefaultWaveSize(const MCSubtargetInfo &STI,
49+
MCContext &Ctx) {
50+
if (!STI.hasFeature(AMDGPU::FeatureWavefrontSize64) &&
51+
!STI.hasFeature(AMDGPU::FeatureWavefrontSize32)) {
52+
MCSubtargetInfo &STICopy = Ctx.getSubtargetCopy(STI);
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// If there is no default wave size it must be a generation before gfx10,
54+
// these have FeatureWavefrontSize64 in their definition already. For gfx10+
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// set wave32 as a default.
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STICopy.ToggleFeature(AMDGPU::FeatureWavefrontSize32);
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return STICopy;
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}
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return STI;
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}
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AMDGPUDisassembler::AMDGPUDisassembler(const MCSubtargetInfo &STI,
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MCContext &Ctx, MCInstrInfo const *MCII)
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: MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()),
51-
MAI(*Ctx.getAsmInfo()), TargetMaxInstBytes(MAI.getMaxInstLength(&STI)),
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: MCDisassembler(addDefaultWaveSize(STI, Ctx), Ctx), MCII(MCII),
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MRI(*Ctx.getRegisterInfo()), MAI(*Ctx.getAsmInfo()),
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TargetMaxInstBytes(MAI.getMaxInstLength(&STI)),
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CodeObjectVersion(AMDGPU::getDefaultAMDHSACodeObjectVersion()) {
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// ToDo: AMDGPUDisassembler supports only VI ISA.
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if (!STI.hasFeature(AMDGPU::FeatureGCN3Encoding) && !isGFX10Plus())

‎llvm/test/CodeGen/AMDGPU/check-subtarget-features.ll

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Original file line numberDiff line numberDiff line change
@@ -1,5 +1,3 @@
1-
; RUN: not llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,-wavefrontsize64 < %s 2>&1 | FileCheck %s -check-prefix=ERR -implicit-check-not=error:
2-
; RUN: not llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,-wavefrontsize64 < %s 2>&1 | FileCheck %s -check-prefix=ERR -implicit-check-not=error:
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; RUN: not llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,+wavefrontsize64 < %s 2>&1 | FileCheck %s -check-prefix=ERR -implicit-check-not=error:
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; RUN: not llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,+wavefrontsize64 < %s 2>&1 | FileCheck %s -check-prefix=ERR -implicit-check-not=error:
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‎llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wavefrontsize.ll

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1,19 +1,19 @@
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; RUN: llc -mtriple=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,W64 %s
2-
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,W32 %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,W64 %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -verify-machineinstrs -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GCN,W32 %s
5-
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,W64 %s
2+
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,W32 %s
3+
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize64 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,W64 %s
4+
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32 -verify-machineinstrs -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GCN,W32 %s
5+
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,W64 %s
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; RUN: opt -O3 -S < %s | FileCheck -check-prefix=OPT %s
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; RUN: opt -mtriple=amdgcn-- -O3 -S < %s | FileCheck -check-prefix=OPT %s
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; RUN: opt -mtriple=amdgcn-- -O3 -mattr=+wavefrontsize32 -S < %s | FileCheck -check-prefix=OPT %s
1010
; RUN: opt -mtriple=amdgcn-- -passes='default<O3>' -mattr=+wavefrontsize32 -S < %s | FileCheck -check-prefix=OPT %s
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; RUN: opt -mtriple=amdgcn-- -O3 -mattr=+wavefrontsize64 -S < %s | FileCheck -check-prefix=OPT %s
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; RUN: opt -mtriple=amdgcn-- -mcpu=tonga -O3 -S < %s | FileCheck -check-prefix=OPT %s
13-
; RUN: opt -mtriple=amdgcn-- -mcpu=gfx1010 -O3 -mattr=+wavefrontsize32,-wavefrontsize64 -S < %s | FileCheck -check-prefix=OPT %s
14-
; RUN: opt -mtriple=amdgcn-- -mcpu=gfx1010 -O3 -mattr=-wavefrontsize32,+wavefrontsize64 -S < %s | FileCheck -check-prefix=OPT %s
15-
; RUN: opt -mtriple=amdgcn-- -mcpu=gfx1100 -O3 -mattr=+wavefrontsize32,-wavefrontsize64 -S < %s | FileCheck -check-prefix=OPT %s
16-
; RUN: opt -mtriple=amdgcn-- -mcpu=gfx1100 -O3 -mattr=-wavefrontsize32,+wavefrontsize64 -S < %s | FileCheck -check-prefix=OPT %s
13+
; RUN: opt -mtriple=amdgcn-- -mcpu=gfx1010 -O3 -mattr=+wavefrontsize32 -S < %s | FileCheck -check-prefix=OPT %s
14+
; RUN: opt -mtriple=amdgcn-- -mcpu=gfx1010 -O3 -mattr=+wavefrontsize64 -S < %s | FileCheck -check-prefix=OPT %s
15+
; RUN: opt -mtriple=amdgcn-- -mcpu=gfx1100 -O3 -mattr=+wavefrontsize32 -S < %s | FileCheck -check-prefix=OPT %s
16+
; RUN: opt -mtriple=amdgcn-- -mcpu=gfx1100 -O3 -mattr=+wavefrontsize64 -S < %s | FileCheck -check-prefix=OPT %s
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1818
; GCN-LABEL: {{^}}fold_wavefrontsize:
1919
; OPT-LABEL: define amdgpu_kernel void @fold_wavefrontsize(

‎llvm/test/CodeGen/AMDGPU/unknown-processor.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
; RUN: not llc -mtriple=amdgcn-- -mcpu=unknown -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=ERROR -check-prefix=GCN %s
1+
; RUN: llc -mtriple=amdgcn-- -mcpu=unknown -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=ERROR -check-prefix=GCN %s
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; RUN: llc -mtriple=r600-- -mcpu=unknown -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=ERROR -check-prefix=R600 %s
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target datalayout = "A5"
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