Update RISCVOptWInstrs

Author: lukel97

llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp

@@ -366,13 +366,7 @@ static bool isSignExtendingOpW(const MachineInstr &MI,
     return MI.getOperand(1).getReg() == RISCV::X0;
   case RISCV::PseudoAtomicLoadNand32:
     return true;
-  case RISCV::PseudoVMV_X_S_MF8:
-  case RISCV::PseudoVMV_X_S_MF4:
-  case RISCV::PseudoVMV_X_S_MF2:
-  case RISCV::PseudoVMV_X_S_M1:
-  case RISCV::PseudoVMV_X_S_M2:
-  case RISCV::PseudoVMV_X_S_M4:
-  case RISCV::PseudoVMV_X_S_M8: {
+  case RISCV::PseudoVMV_X_S: {
     // vmv.x.s has at least 33 sign bits if log2(sew) <= 5.
     int64_t Log2SEW = MI.getOperand(2).getImm();
     assert(Log2SEW >= 3 && Log2SEW <= 6 && "Unexpected Log2SEW");