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[WebAssembly] Implement SIMD signselect instructions
As proposed in WebAssembly/simd#124, using the opcodes adopted by V8 in https://chromium-review.googlesource.com/c/v8/v8/+/2486235/2/src/wasm/wasm-opcodes.h. Uses new builtin functions and a new target intrinsic exclusively to ensure that the new instructions are only emitted when a user explicitly opts in to using them since they are still in the prototyping and evaluation phase. Differential Revision: https://reviews.llvm.org/D90357
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‎clang/include/clang/Basic/BuiltinsWebAssembly.def

+6
Original file line numberDiff line numberDiff line change
@@ -134,6 +134,12 @@ TARGET_BUILTIN(__builtin_wasm_extmul_low_i32x4_u_i64x2, "V2ULLiV4UiV4Ui", "nc",
134134
TARGET_BUILTIN(__builtin_wasm_extmul_high_i32x4_u_i64x2, "V2ULLiV4UiV4Ui", "nc", "simd128")
135135

136136
TARGET_BUILTIN(__builtin_wasm_bitselect, "V4iV4iV4iV4i", "nc", "simd128")
137+
138+
TARGET_BUILTIN(__builtin_wasm_signselect_i8x16, "V16ScV16ScV16ScV16Sc", "nc", "simd128")
139+
TARGET_BUILTIN(__builtin_wasm_signselect_i16x8, "V8sV8sV8sV8s", "nc", "simd128")
140+
TARGET_BUILTIN(__builtin_wasm_signselect_i32x4, "V4iV4iV4iV4i", "nc", "simd128")
141+
TARGET_BUILTIN(__builtin_wasm_signselect_i64x2, "V2LLiV2LLiV2LLiV2LLi", "nc", "simd128")
142+
137143
TARGET_BUILTIN(__builtin_wasm_shuffle_v8x16, "V16ScV16ScV16ScIiIiIiIiIiIiIiIiIiIiIiIiIiIiIiIi", "nc", "simd128")
138144

139145
TARGET_BUILTIN(__builtin_wasm_any_true_i8x16, "iV16Sc", "nc", "simd128")

‎clang/lib/CodeGen/CGBuiltin.cpp

+11
Original file line numberDiff line numberDiff line change
@@ -16675,6 +16675,17 @@ Value *CodeGenFunction::EmitWebAssemblyBuiltinExpr(unsigned BuiltinID,
1667516675
CGM.getIntrinsic(Intrinsic::wasm_bitselect, ConvertType(E->getType()));
1667616676
return Builder.CreateCall(Callee, {V1, V2, C});
1667716677
}
16678+
case WebAssembly::BI__builtin_wasm_signselect_i8x16:
16679+
case WebAssembly::BI__builtin_wasm_signselect_i16x8:
16680+
case WebAssembly::BI__builtin_wasm_signselect_i32x4:
16681+
case WebAssembly::BI__builtin_wasm_signselect_i64x2: {
16682+
Value *V1 = EmitScalarExpr(E->getArg(0));
16683+
Value *V2 = EmitScalarExpr(E->getArg(1));
16684+
Value *C = EmitScalarExpr(E->getArg(2));
16685+
Function *Callee =
16686+
CGM.getIntrinsic(Intrinsic::wasm_signselect, ConvertType(E->getType()));
16687+
return Builder.CreateCall(Callee, {V1, V2, C});
16688+
}
1667816689
case WebAssembly::BI__builtin_wasm_dot_s_i32x4_i16x8: {
1667916690
Value *LHS = EmitScalarExpr(E->getArg(0));
1668016691
Value *RHS = EmitScalarExpr(E->getArg(1));

‎clang/test/CodeGen/builtins-wasm.c

+28
Original file line numberDiff line numberDiff line change
@@ -622,6 +622,34 @@ i32x4 bitselect(i32x4 x, i32x4 y, i32x4 c) {
622622
// WEBASSEMBLY-NEXT: ret
623623
}
624624

625+
i8x16 signselect_i8x16(i8x16 x, i8x16 y, i8x16 c) {
626+
return __builtin_wasm_signselect_i8x16(x, y, c);
627+
// WEBASSEMBLY: call <16 x i8> @llvm.wasm.signselect.v16i8(
628+
// WEBASSEMBLY-SAME: <16 x i8> %x, <16 x i8> %y, <16 x i8> %c)
629+
// WEBASSEMBLY-NEXT: ret
630+
}
631+
632+
i16x8 signselect_i16x8(i16x8 x, i16x8 y, i16x8 c) {
633+
return __builtin_wasm_signselect_i16x8(x, y, c);
634+
// WEBASSEMBLY: call <8 x i16> @llvm.wasm.signselect.v8i16(
635+
// WEBASSEMBLY-SAME: <8 x i16> %x, <8 x i16> %y, <8 x i16> %c)
636+
// WEBASSEMBLY-NEXT: ret
637+
}
638+
639+
i32x4 signselect_i32x4(i32x4 x, i32x4 y, i32x4 c) {
640+
return __builtin_wasm_signselect_i32x4(x, y, c);
641+
// WEBASSEMBLY: call <4 x i32> @llvm.wasm.signselect.v4i32(
642+
// WEBASSEMBLY-SAME: <4 x i32> %x, <4 x i32> %y, <4 x i32> %c)
643+
// WEBASSEMBLY-NEXT: ret
644+
}
645+
646+
i64x2 signselect_i64x2(i64x2 x, i64x2 y, i64x2 c) {
647+
return __builtin_wasm_signselect_i64x2(x, y, c);
648+
// WEBASSEMBLY: call <2 x i64> @llvm.wasm.signselect.v2i64(
649+
// WEBASSEMBLY-SAME: <2 x i64> %x, <2 x i64> %y, <2 x i64> %c)
650+
// WEBASSEMBLY-NEXT: ret
651+
}
652+
625653
i8x16 popcnt(i8x16 x) {
626654
return __builtin_wasm_popcnt_i8x16(x);
627655
// WEBASSEMBLY: call <16 x i8> @llvm.wasm.popcnt(<16 x i8> %x)

‎llvm/include/llvm/IR/IntrinsicsWebAssembly.td

+5
Original file line numberDiff line numberDiff line change
@@ -276,6 +276,11 @@ def int_wasm_extmul_high_unsigned :
276276
[LLVMSubdivide2VectorType<0>, LLVMSubdivide2VectorType<0>],
277277
[IntrNoMem, IntrSpeculatable]>;
278278

279+
def int_wasm_signselect :
280+
Intrinsic<[llvm_anyvector_ty],
281+
[LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
282+
[IntrNoMem, IntrSpeculatable]>;
283+
279284
//===----------------------------------------------------------------------===//
280285
// Thread-local storage intrinsics
281286
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

+17
Original file line numberDiff line numberDiff line change
@@ -747,6 +747,23 @@ def : Pat<(select
747747
)>;
748748
} // foreach vec_t
749749

750+
// Sign select
751+
multiclass SIMDSignSelect<ValueType vec_t, string vec, bits<32> simdop> {
752+
defm SIGNSELECT_#vec_t :
753+
SIMD_I<(outs V128:$dst), (ins V128:$v1, V128:$v2, V128:$c), (outs), (ins),
754+
[(set (vec_t V128:$dst),
755+
(vec_t (int_wasm_signselect
756+
(vec_t V128:$v1), (vec_t V128:$v2), (vec_t V128:$c)
757+
))
758+
)],
759+
vec#".signselect\t$dst, $v1, $v2, $c", vec#".signselect", simdop>;
760+
}
761+
762+
defm : SIMDSignSelect<v16i8, "i8x16", 125>;
763+
defm : SIMDSignSelect<v8i16, "i16x8", 126>;
764+
defm : SIMDSignSelect<v4i32, "i32x4", 127>;
765+
defm : SIMDSignSelect<v2i64, "i64x2", 148>;
766+
750767
//===----------------------------------------------------------------------===//
751768
// Integer unary arithmetic
752769
//===----------------------------------------------------------------------===//

‎llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll

+48
Original file line numberDiff line numberDiff line change
@@ -127,6 +127,18 @@ define <16 x i8> @bitselect_v16i8(<16 x i8> %v1, <16 x i8> %v2, <16 x i8> %c) {
127127
ret <16 x i8> %a
128128
}
129129

130+
; CHECK-LABEL: signselect_v16i8:
131+
; SIMD128-NEXT: .functype signselect_v16i8 (v128, v128, v128) -> (v128){{$}}
132+
; SIMD128-NEXT: i8x16.signselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
133+
; SIMD128-NEXT: return $pop[[R]]{{$}}
134+
declare <16 x i8> @llvm.wasm.signselect.v16i8(<16 x i8>, <16 x i8>, <16 x i8>)
135+
define <16 x i8> @signselect_v16i8(<16 x i8> %v1, <16 x i8> %v2, <16 x i8> %c) {
136+
%a = call <16 x i8> @llvm.wasm.signselect.v16i8(
137+
<16 x i8> %v1, <16 x i8> %v2, <16 x i8> %c
138+
)
139+
ret <16 x i8> %a
140+
}
141+
130142
; CHECK-LABEL: narrow_signed_v16i8:
131143
; SIMD128-NEXT: .functype narrow_signed_v16i8 (v128, v128) -> (v128){{$}}
132144
; SIMD128-NEXT: i8x16.narrow_i16x8_s $push[[R:[0-9]+]]=, $0, $1{{$}}
@@ -339,6 +351,18 @@ define <8 x i16> @bitselect_v8i16(<8 x i16> %v1, <8 x i16> %v2, <8 x i16> %c) {
339351
ret <8 x i16> %a
340352
}
341353

354+
; CHECK-LABEL: signselect_v8i16:
355+
; SIMD128-NEXT: .functype signselect_v8i16 (v128, v128, v128) -> (v128){{$}}
356+
; SIMD128-NEXT: i16x8.signselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
357+
; SIMD128-NEXT: return $pop[[R]]{{$}}
358+
declare <8 x i16> @llvm.wasm.signselect.v8i16(<8 x i16>, <8 x i16>, <8 x i16>)
359+
define <8 x i16> @signselect_v8i16(<8 x i16> %v1, <8 x i16> %v2, <8 x i16> %c) {
360+
%a = call <8 x i16> @llvm.wasm.signselect.v8i16(
361+
<8 x i16> %v1, <8 x i16> %v2, <8 x i16> %c
362+
)
363+
ret <8 x i16> %a
364+
}
365+
342366
; CHECK-LABEL: narrow_signed_v8i16:
343367
; SIMD128-NEXT: .functype narrow_signed_v8i16 (v128, v128) -> (v128){{$}}
344368
; SIMD128-NEXT: i16x8.narrow_i32x4_s $push[[R:[0-9]+]]=, $0, $1{{$}}
@@ -467,6 +491,18 @@ define <4 x i32> @bitselect_v4i32(<4 x i32> %v1, <4 x i32> %v2, <4 x i32> %c) {
467491
ret <4 x i32> %a
468492
}
469493

494+
; CHECK-LABEL: signselect_v4i32:
495+
; SIMD128-NEXT: .functype signselect_v4i32 (v128, v128, v128) -> (v128){{$}}
496+
; SIMD128-NEXT: i32x4.signselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
497+
; SIMD128-NEXT: return $pop[[R]]{{$}}
498+
declare <4 x i32> @llvm.wasm.signselect.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
499+
define <4 x i32> @signselect_v4i32(<4 x i32> %v1, <4 x i32> %v2, <4 x i32> %c) {
500+
%a = call <4 x i32> @llvm.wasm.signselect.v4i32(
501+
<4 x i32> %v1, <4 x i32> %v2, <4 x i32> %c
502+
)
503+
ret <4 x i32> %a
504+
}
505+
470506
; CHECK-LABEL: trunc_sat_s_v4i32:
471507
; NO-SIMD128-NOT: f32x4
472508
; SIMD128-NEXT: .functype trunc_sat_s_v4i32 (v128) -> (v128){{$}}
@@ -572,6 +608,18 @@ define <2 x i64> @bitselect_v2i64(<2 x i64> %v1, <2 x i64> %v2, <2 x i64> %c) {
572608
ret <2 x i64> %a
573609
}
574610

611+
; CHECK-LABEL: signselect_v2i64:
612+
; SIMD128-NEXT: .functype signselect_v2i64 (v128, v128, v128) -> (v128){{$}}
613+
; SIMD128-NEXT: i64x2.signselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
614+
; SIMD128-NEXT: return $pop[[R]]{{$}}
615+
declare <2 x i64> @llvm.wasm.signselect.v2i64(<2 x i64>, <2 x i64>, <2 x i64>)
616+
define <2 x i64> @signselect_v2i64(<2 x i64> %v1, <2 x i64> %v2, <2 x i64> %c) {
617+
%a = call <2 x i64> @llvm.wasm.signselect.v2i64(
618+
<2 x i64> %v1, <2 x i64> %v2, <2 x i64> %c
619+
)
620+
ret <2 x i64> %a
621+
}
622+
575623
; ==============================================================================
576624
; 4 x f32
577625
; ==============================================================================

‎llvm/test/MC/WebAssembly/simd-encodings.s

+12
Original file line numberDiff line numberDiff line change
@@ -694,4 +694,16 @@ main:
694694
# CHECK: i64x2.extmul_high_i32x4_u # encoding: [0xfd,0xd7,0x01]
695695
i64x2.extmul_high_i32x4_u
696696

697+
# CHECK: i8x16.signselect # encoding: [0xfd,0x7d]
698+
i8x16.signselect
699+
700+
# CHECK: i16x8.signselect # encoding: [0xfd,0x7e]
701+
i16x8.signselect
702+
703+
# CHECK: i32x4.signselect # encoding: [0xfd,0x7f]
704+
i32x4.signselect
705+
706+
# CHECK: i64x2.signselect # encoding: [0xfd,0x94,0x01]
707+
i64x2.signselect
708+
697709
end_function

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