[PowerPC] Use MIR test so that it's not affected by instruction selection. NFC.

Author: Kai Luo

llvm/test/CodeGen/PowerPC/aix-csr-alloc.ll

@@ -0,0 +1,21 @@
+# REQUIRES: asserts
+# RUN: llc -verify-machineinstrs -simplify-mir -mtriple=powerpc-ibm-aix-xcoff \
+# RUN:   -debug-only=regalloc %s -o - 2>&1 | FileCheck %s
+
+---
+name: i32
+alignment: 4
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+    liveins: $r3
+    %0:gprc = COPY $r3
+    %1:gprc_and_gprc_nor0 = COPY $r3
+    %2:gprc = ADD4 %0, %1
+    $r3 = COPY %2
+    BLR implicit $lr, implicit undef $rm, implicit $r3
+...
+
+# CHECK-DAG: AllocationOrder(GPRC) = [ $r3 $r4 $r5 $r6 $r7 $r8 $r9 $r10 $r11 $r12 $r0 $r31 $r30 $r29 $r28 $r27 $r26 $r25 $r24 $r23 $r22 $r21 $r20 $r19 $r18 $r17 $r16 $r15 $r14 $r13 ]
+# CHECK-DAG: AllocationOrder(F4RC) = [ $f0 $f1 $f2 $f3 $f4 $f5 $f6 $f7 $f8 $f9 $f10 $f11 $f12 $f13 $f31 $f30 $f29 $f28 $f27 $f26 $f25 $f24 $f23 $f22 $f21 $f20 $f19 $f18 $f17 $f16 $f15 $f14 ]
+# CHECK-DAG: AllocationOrder(GPRC_and_GPRC_NOR0) = [ $r3 $r4 $r5 $r6 $r7 $r8 $r9 $r10 $r11 $r12 $r31 $r30 $r29 $r28 $r27 $r26 $r25 $r24 $r23 $r22 $r21 $r20 $r19 $r18 $r17 $r16 $r15 $r14 $r13 ]

llvm/test/CodeGen/PowerPC/aix-csr-alloc.mir

@@ -0,0 +1,22 @@
+# REQUIRES: asserts
+# RUN: llc -verify-machineinstrs -simplify-mir -mtriple=powerpc64-ibm-aix-xcoff \
+# RUN:   -debug-only=regalloc %s -o - 2>&1 | FileCheck %s
+
+---
+name: i64
+alignment: 4
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+    liveins: $x3, $x4
+    %0: g8rc_and_g8rc_nox0 = COPY $x3
+    %1:g8rc = LD 0, %0
+    %2:f8rc = LFS 0, $x4
+    $x3 = COPY %1
+    $f1 = COPY %2
+    BLR8 implicit $lr8, implicit undef $rm, implicit $x3, implicit $f1
+...
+# CHECK-DAG: AllocationOrder(VFRC) = [ $vf2 $vf3 $vf4 $vf5 $vf0 $vf1 $vf6 $vf7 $vf8 $vf9 $vf10 $vf11 $vf12 $vf13 $vf14 $vf15 $vf16 $vf17 $vf18 $vf19 $vf31 $vf30 $vf29 $vf28 $vf27 $vf26 $vf25 $vf24 $vf23 $vf22 $vf21 $vf20 ]
+# CHECK-DAG: AllocationOrder(G8RC_and_G8RC_NOX0) = [ $x3 $x4 $x5 $x6 $x7 $x8 $x9 $x10 $x11 $x12 $x31 $x30 $x29 $x28 $x27 $x26 $x25 $x24 $x23 $x22 $x21 $x20 $x19 $x18 $x17 $x16 $x15 $x1
+# CHECK-DAG: 4 ]
+# CHECK-DAG: AllocationOrder(F8RC) = [ $f0 $f1 $f2 $f3 $f4 $f5 $f6 $f7 $f8 $f9 $f10 $f11 $f12 $f13 $f31 $f30 $f29 $f28 $f27 $f26 $f25 $f24 $f23 $f22 $f21 $f20 $f19 $f18 $f17 $f16 $f15 $f14 ]