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| 1 | +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 |
| 2 | +; RUN: llc < %s -mtriple=thumbv7-- | FileCheck %s |
| 3 | + |
| 4 | +; Regression from #92576 - ensure abds doesn't get truncated after type legalisation |
| 5 | + |
| 6 | +define void @vp8_rd_pick_inter_mode() { |
| 7 | +; CHECK-LABEL: vp8_rd_pick_inter_mode: |
| 8 | +; CHECK: @ %bb.0: |
| 9 | +; CHECK-NEXT: push {r4, lr} |
| 10 | +; CHECK-NEXT: movs r4, #0 |
| 11 | +; CHECK-NEXT: ldr r0, [r0] |
| 12 | +; CHECK-NEXT: ldr r2, [r4] |
| 13 | +; CHECK-NEXT: movs r1, #180 |
| 14 | +; CHECK-NEXT: str r0, [r1] |
| 15 | +; CHECK-NEXT: movs r1, #188 |
| 16 | +; CHECK-NEXT: sxth r0, r0 |
| 17 | +; CHECK-NEXT: str r2, [r1] |
| 18 | +; CHECK-NEXT: sxth r1, r2 |
| 19 | +; CHECK-NEXT: subs r0, r0, r1 |
| 20 | +; CHECK-NEXT: it mi |
| 21 | +; CHECK-NEXT: rsbmi r0, r0, #0 |
| 22 | +; CHECK-NEXT: bl use |
| 23 | +; CHECK-NEXT: ldrsh.w r0, [r4] |
| 24 | +; CHECK-NEXT: ldrsh.w r1, [r0] |
| 25 | +; CHECK-NEXT: subs r0, r1, r0 |
| 26 | +; CHECK-NEXT: it mi |
| 27 | +; CHECK-NEXT: rsbmi r0, r0, #0 |
| 28 | +; CHECK-NEXT: bl use |
| 29 | + %gep180 = getelementptr inbounds i8, ptr null, i32 180 |
| 30 | + %gep188 = getelementptr inbounds i8, ptr null, i32 188 |
| 31 | + %i0 = load i32, ptr poison, align 4 |
| 32 | + store i32 %i0, ptr %gep180, align 4 |
| 33 | + %i1 = load i32, ptr null, align 4 |
| 34 | + store i32 %i1, ptr %gep188, align 4 |
| 35 | + %sext.i0 = shl i32 %i0, 16 |
| 36 | + %sext.i1 = shl i32 %i1, 16 |
| 37 | + %conv.i0 = ashr exact i32 %sext.i0, 16 |
| 38 | + %conv.i1 = ashr exact i32 %sext.i1, 16 |
| 39 | + %sub.i01 = sub nsw i32 %conv.i0, %conv.i1 |
| 40 | + %i2 = call i32 @llvm.abs.i32(i32 %sub.i01, i1 true) |
| 41 | + call fastcc void @use(i32 %i2) |
| 42 | + |
| 43 | + %i3 = load i16, ptr poison, align 4 |
| 44 | + %i4 = load i16, ptr null, align 4 |
| 45 | + %conv.i3 = sext i16 %i3 to i32 |
| 46 | + %conv.i4 = sext i16 %i4 to i32 |
| 47 | + %sub.i34 = sub nsw i32 %conv.i3, %conv.i4 |
| 48 | + %i5 = call i32 @llvm.abs.i32(i32 %sub.i34, i1 true) |
| 49 | + call fastcc void @use(i32 %i5) |
| 50 | + unreachable |
| 51 | +} |
| 52 | +declare void @use(i32) |
| 53 | + |
| 54 | +attributes #0 = { "target-features"="+armv7-a,+d32,+dsp,+fp64,+neon,+thumb-mode,+vfp2,+vfp2sp,+vfp3,+vfp3d16,+vfp3d16sp,+vfp3sp,-aes,-fp-armv8,-fp-armv8d16,-fp-armv8d16sp,-fp-armv8sp,-fp16,-fp16fml,-fullfp16,-sha2,-vfp4,-vfp4d16,-vfp4d16sp,-vfp4sp" } |
| 55 | +attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } |
| 56 | + |
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