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Revert "[GlobalISel] GIntrinsic subclass to represent intrinsics in Generic Machine IR"
This reverts commit baa3386. The changes did not cover all occurrences of the deteleted function MachineInstr::getIntrinsicID().
1 parent baa3386 commit d0f7850

13 files changed

+51
-85
lines changed

‎llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h

Lines changed: 0 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -358,29 +358,6 @@ class GAddSubCarryInOut : public GAddSubCarryOut {
358358
}
359359
};
360360

361-
/// Represents a call to an intrinsic.
362-
class GIntrinsic final : public GenericMachineInstr {
363-
public:
364-
Intrinsic::ID getIntrinsicID() const {
365-
return getOperand(getNumExplicitDefs()).getIntrinsicID();
366-
}
367-
368-
bool is(Intrinsic::ID ID) const { return getIntrinsicID() == ID; }
369-
bool hasSideEffects() const {
370-
return getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS;
371-
}
372-
373-
static bool classof(const MachineInstr *MI) {
374-
switch (MI->getOpcode()) {
375-
case TargetOpcode::G_INTRINSIC:
376-
case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS:
377-
return true;
378-
default:
379-
return false;
380-
}
381-
}
382-
};
383-
384361
} // namespace llvm
385362

386363
#endif // LLVM_CODEGEN_GLOBALISEL_GENERICMACHINEINSTRS_H

‎llvm/include/llvm/CodeGen/MachineInstr.h

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1930,6 +1930,12 @@ class MachineInstr
19301930
/// and point them to \p Reg instead.
19311931
void changeDebugValuesDefReg(Register Reg);
19321932

1933+
/// Returns the Intrinsic::ID for this instruction.
1934+
/// \pre Must have an intrinsic ID operand.
1935+
unsigned getIntrinsicID() const {
1936+
return getOperand(getNumExplicitDefs()).getIntrinsicID();
1937+
}
1938+
19331939
/// Sets all register debug operands in this debug value instruction to be
19341940
/// undef.
19351941
void setDebugValueUndef() {

‎llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,6 @@
99
#include "AMDGPUCombinerHelper.h"
1010
#include "GCNSubtarget.h"
1111
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
12-
#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
1312
#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
1413
#include "llvm/IR/IntrinsicsAMDGPU.h"
1514
#include "llvm/Target/TargetMachine.h"
@@ -43,7 +42,7 @@ static bool fnegFoldsIntoMI(const MachineInstr &MI) {
4342
case AMDGPU::G_AMDGPU_FMAX_LEGACY:
4443
return true;
4544
case AMDGPU::G_INTRINSIC: {
46-
unsigned IntrinsicID = cast<GIntrinsic>(MI).getIntrinsicID();
45+
unsigned IntrinsicID = MI.getIntrinsicID();
4746
switch (IntrinsicID) {
4847
case Intrinsic::amdgcn_rcp:
4948
case Intrinsic::amdgcn_rcp_legacy:
@@ -93,7 +92,7 @@ static bool hasSourceMods(const MachineInstr &MI) {
9392
case AMDGPU::G_PHI:
9493
return false;
9594
case AMDGPU::G_INTRINSIC: {
96-
unsigned IntrinsicID = cast<GIntrinsic>(MI).getIntrinsicID();
95+
unsigned IntrinsicID = MI.getIntrinsicID();
9796
switch (IntrinsicID) {
9897
case Intrinsic::amdgcn_interp_p1:
9998
case Intrinsic::amdgcn_interp_p2:
@@ -229,7 +228,7 @@ bool AMDGPUCombinerHelper::matchFoldableFneg(MachineInstr &MI,
229228
case AMDGPU::G_AMDGPU_RCP_IFLAG:
230229
return true;
231230
case AMDGPU::G_INTRINSIC: {
232-
unsigned IntrinsicID = cast<GIntrinsic>(MatchInfo)->getIntrinsicID();
231+
unsigned IntrinsicID = MatchInfo->getIntrinsicID();
233232
switch (IntrinsicID) {
234233
case Intrinsic::amdgcn_rcp:
235234
case Intrinsic::amdgcn_rcp_legacy:
@@ -328,7 +327,7 @@ void AMDGPUCombinerHelper::applyFoldableFneg(MachineInstr &MI,
328327
NegateOperand(MatchInfo->getOperand(1));
329328
break;
330329
case AMDGPU::G_INTRINSIC: {
331-
unsigned IntrinsicID = cast<GIntrinsic>(MatchInfo)->getIntrinsicID();
330+
unsigned IntrinsicID = MatchInfo->getIntrinsicID();
332331
switch (IntrinsicID) {
333332
case Intrinsic::amdgcn_rcp:
334333
case Intrinsic::amdgcn_rcp_legacy:

‎llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.cpp

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,6 @@
1414

1515
#include "AMDGPUInstrInfo.h"
1616
#include "AMDGPU.h"
17-
#include "llvm/CodeGen/MachineInstr.h"
1817
#include "llvm/CodeGen/MachineMemOperand.h"
1918
#include "llvm/IR/Constants.h"
2019
#include "llvm/IR/Instruction.h"
@@ -27,9 +26,6 @@ using namespace llvm;
2726

2827
AMDGPUInstrInfo::AMDGPUInstrInfo(const GCNSubtarget &ST) { }
2928

30-
Intrinsic::ID AMDGPU::getIntrinsicID(const MachineInstr &I) {
31-
return I.getOperand(I.getNumExplicitDefs()).getIntrinsicID();
32-
}
3329

3430
// TODO: Should largely merge with AMDGPUTTIImpl::isSourceOfDivergence.
3531
bool AMDGPUInstrInfo::isUniformMMO(const MachineMemOperand *MMO) {

‎llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.h

Lines changed: 0 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,6 @@ namespace llvm {
2121

2222
class GCNSubtarget;
2323
class MachineMemOperand;
24-
class MachineInstr;
2524

2625
class AMDGPUInstrInfo {
2726
public:
@@ -32,13 +31,6 @@ class AMDGPUInstrInfo {
3231

3332
namespace AMDGPU {
3433

35-
/// Return the intrinsic ID for opcodes with the G_AMDGPU_INTRIN_ prefix.
36-
///
37-
/// These opcodes have an Intrinsic::ID operand similar to a GIntrinsic. But
38-
/// they are not actual instances of GIntrinsics, so we cannot use
39-
/// GIntrinsic::getIntrinsicID() on them.
40-
unsigned getIntrinsicID(const MachineInstr &I);
41-
4234
struct RsrcIntrinsic {
4335
unsigned Intr;
4436
uint8_t RsrcArg;

‎llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

Lines changed: 7 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,6 @@
2121
#include "Utils/AMDGPUBaseInfo.h"
2222
#include "llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h"
2323
#include "llvm/CodeGen/GlobalISel/GISelKnownBits.h"
24-
#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
2524
#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
2625
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
2726
#include "llvm/CodeGen/MachineFrameInfo.h"
@@ -1002,7 +1001,7 @@ bool AMDGPUInstructionSelector::selectDivScale(MachineInstr &MI) const {
10021001
}
10031002

10041003
bool AMDGPUInstructionSelector::selectG_INTRINSIC(MachineInstr &I) const {
1005-
unsigned IntrinsicID = cast<GIntrinsic>(I).getIntrinsicID();
1004+
unsigned IntrinsicID = I.getIntrinsicID();
10061005
switch (IntrinsicID) {
10071006
case Intrinsic::amdgcn_if_break: {
10081007
MachineBasicBlock *BB = I.getParent();
@@ -2009,7 +2008,7 @@ bool AMDGPUInstructionSelector::selectDSBvhStackIntrinsic(
20092008

20102009
bool AMDGPUInstructionSelector::selectG_INTRINSIC_W_SIDE_EFFECTS(
20112010
MachineInstr &I) const {
2012-
unsigned IntrinsicID = cast<GIntrinsic>(I).getIntrinsicID();
2011+
unsigned IntrinsicID = I.getIntrinsicID();
20132012
switch (IntrinsicID) {
20142013
case Intrinsic::amdgcn_end_cf:
20152014
return selectEndCfIntrinsic(I);
@@ -2690,8 +2689,8 @@ static bool isVCmpResult(Register Reg, MachineRegisterInfo &MRI) {
26902689
return isVCmpResult(MI.getOperand(1).getReg(), MRI) &&
26912690
isVCmpResult(MI.getOperand(2).getReg(), MRI);
26922691

2693-
if (auto *GI = dyn_cast<GIntrinsic>(&MI))
2694-
return GI->is(Intrinsic::amdgcn_class);
2692+
if (Opcode == TargetOpcode::G_INTRINSIC)
2693+
return MI.getIntrinsicID() == Intrinsic::amdgcn_class;
26952694

26962695
return Opcode == AMDGPU::G_ICMP || Opcode == AMDGPU::G_FCMP;
26972696
}
@@ -3253,7 +3252,7 @@ bool AMDGPUInstructionSelector::selectBVHIntrinsic(MachineInstr &MI) const{
32533252

32543253
bool AMDGPUInstructionSelector::selectSMFMACIntrin(MachineInstr &MI) const {
32553254
unsigned Opc;
3256-
switch (cast<GIntrinsic>(MI).getIntrinsicID()) {
3255+
switch (MI.getIntrinsicID()) {
32573256
case Intrinsic::amdgcn_smfmac_f32_16x16x32_f16:
32583257
Opc = AMDGPU::V_SMFMAC_F32_16X16X32_F16_e64;
32593258
break;
@@ -3458,8 +3457,8 @@ bool AMDGPUInstructionSelector::select(MachineInstr &I) {
34583457
case AMDGPU::G_AMDGPU_INTRIN_IMAGE_LOAD_D16:
34593458
case AMDGPU::G_AMDGPU_INTRIN_IMAGE_STORE:
34603459
case AMDGPU::G_AMDGPU_INTRIN_IMAGE_STORE_D16: {
3461-
const AMDGPU::ImageDimIntrinsicInfo *Intr =
3462-
AMDGPU::getImageDimIntrinsicInfo(AMDGPU::getIntrinsicID(I));
3460+
const AMDGPU::ImageDimIntrinsicInfo *Intr
3461+
= AMDGPU::getImageDimIntrinsicInfo(I.getIntrinsicID());
34633462
assert(Intr && "not an image intrinsic with image pseudo");
34643463
return selectImageIntrinsic(I, Intr);
34653464
}

‎llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,6 @@
2121
#include "Utils/AMDGPUBaseInfo.h"
2222
#include "llvm/ADT/ScopeExit.h"
2323
#include "llvm/BinaryFormat/ELF.h"
24-
#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
2524
#include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
2625
#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
2726
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
@@ -6525,7 +6524,7 @@ bool AMDGPULegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
65256524
MachineRegisterInfo &MRI = *B.getMRI();
65266525

65276526
// Replace the use G_BRCOND with the exec manipulate and branch pseudos.
6528-
auto IntrID = cast<GIntrinsic>(MI).getIntrinsicID();
6527+
auto IntrID = MI.getIntrinsicID();
65296528
switch (IntrID) {
65306529
case Intrinsic::amdgcn_if:
65316530
case Intrinsic::amdgcn_else: {

‎llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,6 @@
2222
#include "llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h"
2323
#include "llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h"
2424
#include "llvm/CodeGen/GlobalISel/GISelKnownBits.h"
25-
#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
2625
#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
2726
#include "llvm/CodeGen/MachineDominators.h"
2827
#include "llvm/CodeGen/TargetPassConfig.h"
@@ -269,10 +268,10 @@ bool AMDGPUPostLegalizerCombinerImpl::matchRcpSqrtToRsq(
269268

270269
auto getRcpSrc = [=](const MachineInstr &MI) {
271270
MachineInstr *ResMI = nullptr;
272-
if (auto *GI = dyn_cast<GIntrinsic>(&MI)) {
273-
if (GI->is(Intrinsic::amdgcn_rcp))
274-
ResMI = MRI.getVRegDef(MI.getOperand(2).getReg());
275-
}
271+
if (MI.getOpcode() == TargetOpcode::G_INTRINSIC &&
272+
MI.getIntrinsicID() == Intrinsic::amdgcn_rcp)
273+
ResMI = MRI.getVRegDef(MI.getOperand(2).getReg());
274+
276275
return ResMI;
277276
};
278277

‎llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -337,7 +337,7 @@ AMDGPURegisterBankInfo::addMappingFromTable(
337337
RegisterBankInfo::InstructionMappings
338338
AMDGPURegisterBankInfo::getInstrAlternativeMappingsIntrinsic(
339339
const MachineInstr &MI, const MachineRegisterInfo &MRI) const {
340-
switch (cast<GIntrinsic>(MI).getIntrinsicID()) {
340+
switch (MI.getIntrinsicID()) {
341341
case Intrinsic::amdgcn_readlane: {
342342
static const OpRegBankEntry<3> Table[2] = {
343343
// Perfectly legal.
@@ -378,7 +378,7 @@ RegisterBankInfo::InstructionMappings
378378
AMDGPURegisterBankInfo::getInstrAlternativeMappingsIntrinsicWSideEffects(
379379
const MachineInstr &MI, const MachineRegisterInfo &MRI) const {
380380

381-
switch (cast<GIntrinsic>(MI).getIntrinsicID()) {
381+
switch (MI.getIntrinsicID()) {
382382
case Intrinsic::amdgcn_s_buffer_load: {
383383
static const OpRegBankEntry<2> Table[4] = {
384384
// Perfectly legal.
@@ -2949,7 +2949,7 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
29492949
return;
29502950
}
29512951
case AMDGPU::G_INTRINSIC: {
2952-
switch (cast<GIntrinsic>(MI).getIntrinsicID()) {
2952+
switch (MI.getIntrinsicID()) {
29532953
case Intrinsic::amdgcn_readlane: {
29542954
substituteSimpleCopyRegs(OpdMapper, 2);
29552955

@@ -3019,8 +3019,8 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
30193019
case AMDGPU::G_AMDGPU_INTRIN_IMAGE_LOAD_D16:
30203020
case AMDGPU::G_AMDGPU_INTRIN_IMAGE_STORE:
30213021
case AMDGPU::G_AMDGPU_INTRIN_IMAGE_STORE_D16: {
3022-
const AMDGPU::RsrcIntrinsic *RSrcIntrin =
3023-
AMDGPU::lookupRsrcIntrinsic(AMDGPU::getIntrinsicID(MI));
3022+
const AMDGPU::RsrcIntrinsic *RSrcIntrin
3023+
= AMDGPU::lookupRsrcIntrinsic(MI.getIntrinsicID());
30243024
assert(RSrcIntrin && RSrcIntrin->IsImage);
30253025
// Non-images can have complications from operands that allow both SGPR
30263026
// and VGPR. For now it's too complicated to figure out the final opcode
@@ -3035,7 +3035,7 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
30353035
return;
30363036
}
30373037
case AMDGPU::G_INTRINSIC_W_SIDE_EFFECTS: {
3038-
auto IntrID = cast<GIntrinsic>(MI).getIntrinsicID();
3038+
auto IntrID = MI.getIntrinsicID();
30393039
switch (IntrID) {
30403040
case Intrinsic::amdgcn_ds_ordered_add:
30413041
case Intrinsic::amdgcn_ds_ordered_swap: {
@@ -4198,7 +4198,7 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
41984198
break;
41994199
}
42004200
case AMDGPU::G_INTRINSIC: {
4201-
switch (cast<GIntrinsic>(MI).getIntrinsicID()) {
4201+
switch (MI.getIntrinsicID()) {
42024202
default:
42034203
return getInvalidInstructionMapping();
42044204
case Intrinsic::amdgcn_div_fmas:
@@ -4531,7 +4531,7 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
45314531
case AMDGPU::G_AMDGPU_INTRIN_IMAGE_LOAD_D16:
45324532
case AMDGPU::G_AMDGPU_INTRIN_IMAGE_STORE:
45334533
case AMDGPU::G_AMDGPU_INTRIN_IMAGE_STORE_D16: {
4534-
auto IntrID = AMDGPU::getIntrinsicID(MI);
4534+
auto IntrID = MI.getIntrinsicID();
45354535
const AMDGPU::RsrcIntrinsic *RSrcIntrin = AMDGPU::lookupRsrcIntrinsic(IntrID);
45364536
assert(RSrcIntrin && "missing RsrcIntrinsic for image intrinsic");
45374537
// Non-images can have complications from operands that allow both SGPR
@@ -4560,7 +4560,7 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
45604560
break;
45614561
}
45624562
case AMDGPU::G_INTRINSIC_W_SIDE_EFFECTS: {
4563-
auto IntrID = cast<GIntrinsic>(MI).getIntrinsicID();
4563+
auto IntrID = MI.getIntrinsicID();
45644564
switch (IntrID) {
45654565
case Intrinsic::amdgcn_s_getreg:
45664566
case Intrinsic::amdgcn_s_memtime:

‎llvm/lib/Target/AMDGPU/SIISelLowering.cpp

Lines changed: 9 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -28,7 +28,6 @@
2828
#include "llvm/CodeGen/ByteProvider.h"
2929
#include "llvm/CodeGen/FunctionLoweringInfo.h"
3030
#include "llvm/CodeGen/GlobalISel/GISelKnownBits.h"
31-
#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
3231
#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
3332
#include "llvm/CodeGen/MachineFrameInfo.h"
3433
#include "llvm/CodeGen/MachineFunction.h"
@@ -11303,7 +11302,7 @@ bool SITargetLowering::isCanonicalized(Register Reg, MachineFunction &MF,
1130311302
return false;
1130411303
return true;
1130511304
case AMDGPU::G_INTRINSIC:
11306-
switch (cast<GIntrinsic>(MI)->getIntrinsicID()) {
11305+
switch (MI->getIntrinsicID()) {
1130711306
case Intrinsic::amdgcn_fmul_legacy:
1130811307
case Intrinsic::amdgcn_fmad_ftz:
1130911308
case Intrinsic::amdgcn_sqrt:
@@ -13737,7 +13736,7 @@ void SITargetLowering::computeKnownBitsForTargetInstr(
1373713736
const MachineInstr *MI = MRI.getVRegDef(R);
1373813737
switch (MI->getOpcode()) {
1373913738
case AMDGPU::G_INTRINSIC: {
13740-
switch (cast<GIntrinsic>(MI)->getIntrinsicID()) {
13739+
switch (MI->getIntrinsicID()) {
1374113740
case Intrinsic::amdgcn_workitem_id_x:
1374213741
knownBitsForWorkitemID(*getSubtarget(), KB, Known, 0);
1374313742
break;
@@ -13802,17 +13801,21 @@ Align SITargetLowering::computeKnownAlignForTargetInstr(
1380213801
GISelKnownBits &KB, Register R, const MachineRegisterInfo &MRI,
1380313802
unsigned Depth) const {
1380413803
const MachineInstr *MI = MRI.getVRegDef(R);
13805-
if (auto *GI = dyn_cast<GIntrinsic>(MI)) {
13804+
switch (MI->getOpcode()) {
13805+
case AMDGPU::G_INTRINSIC:
13806+
case AMDGPU::G_INTRINSIC_W_SIDE_EFFECTS: {
1380613807
// FIXME: Can this move to generic code? What about the case where the call
1380713808
// site specifies a lower alignment?
13808-
Intrinsic::ID IID = GI->getIntrinsicID();
13809+
Intrinsic::ID IID = MI->getIntrinsicID();
1380913810
LLVMContext &Ctx = KB.getMachineFunction().getFunction().getContext();
1381013811
AttributeList Attrs = Intrinsic::getAttributes(Ctx, IID);
1381113812
if (MaybeAlign RetAlign = Attrs.getRetAlignment())
1381213813
return *RetAlign;
1381313814
return Align(1);
1381413815
}
13815-
return Align(1);
13816+
default:
13817+
return Align(1);
13818+
}
1381613819
}
1381713820

1381813821
Align SITargetLowering::getPrefLoopAlignment(MachineLoop *ML) const {

‎llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,6 @@
1818
#include "GCNSubtarget.h"
1919
#include "SIMachineFunctionInfo.h"
2020
#include "llvm/Analysis/ValueTracking.h"
21-
#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
2221
#include "llvm/CodeGen/LiveIntervals.h"
2322
#include "llvm/CodeGen/LiveVariables.h"
2423
#include "llvm/CodeGen/MachineDominators.h"
@@ -8604,8 +8603,9 @@ unsigned SIInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
86048603
InstructionUniformity
86058604
SIInstrInfo::getGenericInstructionUniformity(const MachineInstr &MI) const {
86068605
unsigned opcode = MI.getOpcode();
8607-
if (auto *GI = dyn_cast<GIntrinsic>(&MI)) {
8608-
auto IID = GI->getIntrinsicID();
8606+
if (opcode == AMDGPU::G_INTRINSIC ||
8607+
opcode == AMDGPU::G_INTRINSIC_W_SIDE_EFFECTS) {
8608+
auto IID = static_cast<Intrinsic::ID>(MI.getIntrinsicID());
86098609
if (AMDGPU::isIntrinsicSourceOfDivergence(IID))
86108610
return InstructionUniformity::NeverUniform;
86118611
if (AMDGPU::isIntrinsicAlwaysUniform(IID))

‎llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,6 @@
2121
#include "SPIRVUtils.h"
2222
#include "llvm/ADT/APFloat.h"
2323
#include "llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h"
24-
#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
2524
#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
2625
#include "llvm/CodeGen/MachineInstrBuilder.h"
2726
#include "llvm/CodeGen/MachineRegisterInfo.h"
@@ -1315,7 +1314,7 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg,
13151314
const SPIRVType *ResType,
13161315
MachineInstr &I) const {
13171316
MachineBasicBlock &BB = *I.getParent();
1318-
switch (cast<GIntrinsic>(I).getIntrinsicID()) {
1317+
switch (I.getIntrinsicID()) {
13191318
case Intrinsic::spv_load:
13201319
return selectLoad(ResVReg, ResType, I);
13211320
case Intrinsic::spv_store:

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