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[RISCV] Bump I, F, D, and A extension versions to 20191214 spec version
New versions I2.1, F2.2, D2.2 A2.1 Make F and Zfinx imply Zicsr. Make G imply Zifencei. This should have no impact to generated code. We have no plans to require Zicsr/Zifencei extension to be explicitly enabled to use Zicsr/Zifencei instructions in assembly. See https://reviews.llvm.org/D147183 for documentation regarding what version specification we implement. Reviewed By: asb Differential Revision: https://reviews.llvm.org/D147179
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‎clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -21,10 +21,10 @@ unsigned long test_vlenb(void) {
2121
return __riscv_vlenb();
2222
}
2323
//.
24-
// RV32: attributes #0 = { mustprogress nofree noinline nosync nounwind willreturn memory(read) vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+d,+f,+v,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
24+
// RV32: attributes #0 = { mustprogress nofree noinline nosync nounwind willreturn memory(read) vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+d,+f,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
2525
// RV32: attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(read) }
2626
//.
27-
// RV64: attributes #0 = { mustprogress nofree noinline nosync nounwind willreturn memory(read) vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+v,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
27+
// RV64: attributes #0 = { mustprogress nofree noinline nosync nounwind willreturn memory(read) vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
2828
// RV64: attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(read) }
2929
//.
3030
// RV32: !0 = !{i32 1, !"wchar_size", i32 4}

‎clang/test/Driver/riscv-arch.c

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// RUN: %clang --target=riscv32-unknown-elf -march=rv32i -### %s \
22
// RUN: -fsyntax-only 2>&1 | FileCheck %s
3-
// RUN: %clang --target=riscv32-unknown-elf -march=rv32i2p0 -### %s \
3+
// RUN: %clang --target=riscv32-unknown-elf -march=rv32i2p1 -### %s \
44
// RUN: -fsyntax-only 2>&1 | FileCheck %s
55
// RUN: %clang --target=riscv32-unknown-elf -march=rv32im -### %s \
66
// RUN: -fsyntax-only 2>&1 | FileCheck %s
@@ -70,7 +70,7 @@
7070

7171
// RUN: %clang --target=riscv64-unknown-elf -march=rv64i -### %s \
7272
// RUN: -fsyntax-only 2>&1 | FileCheck %s
73-
// RUN: %clang --target=riscv64-unknown-elf -march=rv64i2p0 -### %s \
73+
// RUN: %clang --target=riscv64-unknown-elf -march=rv64i2p1 -### %s \
7474
// RUN: -fsyntax-only 2>&1 | FileCheck %s
7575
// RUN: %clang --target=riscv64-unknown-elf -march=rv64im -### %s \
7676
// RUN: -fsyntax-only 2>&1 | FileCheck %s
@@ -321,10 +321,10 @@
321321
// RV32-IMINOR-MISS: error: invalid arch name 'rv32i2p',
322322
// RV32-IMINOR-MISS: minor version number missing after 'p' for extension 'i'
323323

324-
// RUN: %clang --target=riscv32-unknown-elf -march=rv32i2p1 -### %s \
324+
// RUN: %clang --target=riscv32-unknown-elf -march=rv32i2p2 -### %s \
325325
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-IMINOR1 %s
326-
// RV32-IMINOR1: error: invalid arch name 'rv32i2p1', unsupported
327-
// RV32-IMINOR1: version number 2.1 for extension 'i'
326+
// RV32-IMINOR1: error: invalid arch name 'rv32i2p2', unsupported
327+
// RV32-IMINOR1: version number 2.2 for extension 'i'
328328

329329
// RUN: %clang --target=riscv32-unknown-elf -march=rv32ixt2p -### %s \
330330
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-XMINOR-MISS %s

‎clang/test/Preprocessor/riscv-target-features.c

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -64,7 +64,7 @@
6464
// RUN: -o - | FileCheck %s
6565
// RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64i -x c -E -dM %s \
6666
// RUN: -o - | FileCheck %s
67-
// CHECK: __riscv_i 2000000{{$}}
67+
// CHECK: __riscv_i 2001000{{$}}
6868

6969
// RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32im -x c -E -dM %s \
7070
// RUN: -o - | FileCheck --check-prefix=CHECK-M-EXT %s
@@ -79,14 +79,14 @@
7979
// RUN: -o - | FileCheck --check-prefix=CHECK-A-EXT %s
8080
// RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64ia -x c -E -dM %s \
8181
// RUN: -o - | FileCheck --check-prefix=CHECK-A-EXT %s
82-
// CHECK-A-EXT: __riscv_a 2000000{{$}}
82+
// CHECK-A-EXT: __riscv_a 2001000{{$}}
8383
// CHECK-A-EXT: __riscv_atomic 1
8484

8585
// RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32if -x c -E -dM %s \
8686
// RUN: -o - | FileCheck --check-prefix=CHECK-F-EXT %s
8787
// RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64if -x c -E -dM %s \
8888
// RUN: -o - | FileCheck --check-prefix=CHECK-F-EXT %s
89-
// CHECK-F-EXT: __riscv_f 2000000{{$}}
89+
// CHECK-F-EXT: __riscv_f 2002000{{$}}
9090
// CHECK-F-EXT: __riscv_fdiv 1
9191
// CHECK-F-EXT: __riscv_flen 32
9292
// CHECK-F-EXT: __riscv_fsqrt 1
@@ -95,7 +95,7 @@
9595
// RUN: -o - | FileCheck --check-prefix=CHECK-D-EXT %s
9696
// RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64ifd -x c -E -dM %s \
9797
// RUN: -o - | FileCheck --check-prefix=CHECK-D-EXT %s
98-
// CHECK-D-EXT: __riscv_d 2000000{{$}}
98+
// CHECK-D-EXT: __riscv_d 2002000{{$}}
9999
// CHECK-D-EXT: __riscv_fdiv 1
100100
// CHECK-D-EXT: __riscv_flen 64
101101
// CHECK-D-EXT: __riscv_fsqrt 1
@@ -214,7 +214,7 @@
214214
// RUN: %clang -target riscv64-unknown-linux-gnu \
215215
// RUN: -march=rv64izfhmin1p0 -x c -E -dM %s \
216216
// RUN: -o - | FileCheck --check-prefix=CHECK-ZFHMIN-EXT %s
217-
// CHECK-ZFHMIN-EXT: __riscv_f 2000000{{$}}
217+
// CHECK-ZFHMIN-EXT: __riscv_f 2002000{{$}}
218218
// CHECK-ZFHMIN-EXT: __riscv_zfhmin 1000000{{$}}
219219

220220
// RUN: %clang -target riscv32-unknown-linux-gnu \
@@ -223,7 +223,7 @@
223223
// RUN: %clang -target riscv64-unknown-linux-gnu \
224224
// RUN: -march=rv64izfh1p0 -x c -E -dM %s \
225225
// RUN: -o - | FileCheck --check-prefix=CHECK-ZFH-EXT %s
226-
// CHECK-ZFH-EXT: __riscv_f 2000000{{$}}
226+
// CHECK-ZFH-EXT: __riscv_f 2002000{{$}}
227227
// CHECK-ZFH-EXT: __riscv_zfh 1000000{{$}}
228228

229229
// RUN: %clang -target riscv32-unknown-linux-gnu \

‎lld/test/ELF/lto/riscv-attributes.ll

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -10,10 +10,10 @@
1010
; CHECK: BuildAttributes {
1111
; CHECK-NEXT: FormatVersion: 0x41
1212
; CHECK-NEXT: Section 1 {
13-
; CHECK-NEXT: SectionLength: 61
13+
; CHECK-NEXT: SectionLength: 70
1414
; CHECK-NEXT: Vendor: riscv
1515
; CHECK-NEXT: Tag: Tag_File (0x1)
16-
; CHECK-NEXT: Size: 51
16+
; CHECK-NEXT: Size: 60
1717
; CHECK-NEXT: FileAttributes {
1818
; CHECK-NEXT: Attribute {
1919
; CHECK-NEXT: Tag: 4
@@ -30,18 +30,18 @@
3030
; CHECK-NEXT: Attribute {
3131
; CHECK-NEXT: Tag: 5
3232
; CHECK-NEXT: TagName: arch
33-
; CHECK-NEXT: Value: rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_zbb1p0
33+
; CHECK-NEXT: Value: rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zbb1p0{{$}}
3434
; CHECK-NEXT: }
3535
; CHECK-NEXT: }
3636
; CHECK-NEXT: }
3737
; CHECK-NEXT: }
3838

3939
;--- 1.s
4040
.attribute 4, 16
41-
.attribute 5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
41+
.attribute 5, "rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0"
4242
;--- 2.s
4343
.attribute 4, 16
44-
.attribute 5, "rv32i2p0_m2p0_f2p0_d2p0_zbb1p0"
44+
.attribute 5, "rv32i2p1_m2p0_f2p2_d2p2_zbb1p0"
4545
.attribute 6, 1
4646

4747
;--- a.ll

‎lld/test/ELF/riscv-attributes.s

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -66,10 +66,10 @@
6666
# CHECK: BuildAttributes {
6767
# CHECK-NEXT: FormatVersion: 0x41
6868
# CHECK-NEXT: Section 1 {
69-
# CHECK-NEXT: SectionLength: 52
69+
# CHECK-NEXT: SectionLength: 61
7070
# CHECK-NEXT: Vendor: riscv
7171
# CHECK-NEXT: Tag: Tag_File (0x1)
72-
# CHECK-NEXT: Size: 42
72+
# CHECK-NEXT: Size: 51
7373
# CHECK-NEXT: FileAttributes {
7474
# CHECK-NEXT: Attribute {
7575
# CHECK-NEXT: Tag: 4
@@ -80,7 +80,7 @@
8080
# CHECK-NEXT: Attribute {
8181
# CHECK-NEXT: Tag: 5
8282
# CHECK-NEXT: TagName: arch
83-
# CHECK-NEXT: Value: rv64i2p0_m2p0_a2p0_f2p0_d2p0_c2p0
83+
# CHECK-NEXT: Value: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0{{$}}
8484
# CHECK-NEXT: }
8585
# CHECK-NEXT: }
8686
# CHECK-NEXT: }
@@ -89,10 +89,10 @@
8989
# CHECK2: BuildAttributes {
9090
# CHECK2-NEXT: FormatVersion: 0x41
9191
# CHECK2-NEXT: Section 1 {
92-
# CHECK2-NEXT: SectionLength: 95
92+
# CHECK2-NEXT: SectionLength: 104
9393
# CHECK2-NEXT: Vendor: riscv
9494
# CHECK2-NEXT: Tag: Tag_File (0x1)
95-
# CHECK2-NEXT: Size: 85
95+
# CHECK2-NEXT: Size: 94
9696
# CHECK2-NEXT: FileAttributes {
9797
# CHECK2-NEXT: Attribute {
9898
# CHECK2-NEXT: Tag: 4
@@ -119,7 +119,7 @@
119119
# CHECK2-NEXT: Attribute {
120120
# CHECK2-NEXT: Tag: 5
121121
# CHECK2-NEXT: TagName: arch
122-
# CHECK2-NEXT: Value: rv64i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_zkt1p0_zve32f1p0_zve32x1p0_zvl32b1p0
122+
# CHECK2-NEXT: Value: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zkt1p0_zve32f1p0_zve32x1p0_zvl32b1p0{{$}}
123123
# CHECK2-NEXT: }
124124
# CHECK2-NEXT: }
125125
# CHECK2-NEXT: }
@@ -136,26 +136,26 @@
136136
# CHECK3-NEXT: Attribute {
137137
# CHECK3-NEXT: Tag: 5
138138
# CHECK3-NEXT: TagName: arch
139-
# CHECK3-NEXT: Value: rv64i99p0
139+
# CHECK3-NEXT: Value: rv64i99p0{{$}}
140140
# CHECK3-NEXT: }
141141
# CHECK3-NEXT: }
142142
# CHECK3-NEXT: }
143143
# CHECK3-NEXT: }
144144

145145
#--- a.s
146146
.attribute stack_align, 16
147-
.attribute arch, "rv64i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
147+
.attribute arch, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0"
148148
.attribute unaligned_access, 0
149149

150150
#--- b.s
151151
.attribute stack_align, 16
152-
.attribute arch, "rv64i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
152+
.attribute arch, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0"
153153
.attribute priv_spec, 2
154154
.attribute priv_spec_minor, 2
155155

156156
#--- c.s
157157
.attribute stack_align, 16
158-
.attribute arch, "rv64i2p0_f2p0_zkt1p0_zve32f1p0_zve32x1p0_zvl32b1p0"
158+
.attribute arch, "rv64i2p1_f2p2_zkt1p0_zve32f1p0_zve32x1p0_zvl32b1p0"
159159
.attribute unaligned_access, 1
160160
.attribute priv_spec, 2
161161
.attribute priv_spec_minor, 2
@@ -172,7 +172,7 @@
172172
# UNRECOGNIZED_EXT1-NEXT: Attribute {
173173
# UNRECOGNIZED_EXT1-NEXT: Tag: 5
174174
# UNRECOGNIZED_EXT1-NEXT: TagName: arch
175-
# UNRECOGNIZED_EXT1-NEXT: Value: rv64i2p0_y2p0
175+
# UNRECOGNIZED_EXT1-NEXT: Value: rv64i2p1_y2p0{{$}}
176176
# UNRECOGNIZED_EXT1-NEXT: }
177177
# UNRECOGNIZED_EXT1-NEXT: }
178178
# UNRECOGNIZED_EXT1-NEXT: }
@@ -185,7 +185,7 @@
185185
.byte 1 # Tag_File
186186
.long .Lend-.Lbegin
187187
.byte 5 # Tag_RISCV_arch
188-
.asciz "rv64i2p0_y2p0"
188+
.asciz "rv64i2p1_y2p0"
189189
.Lend:
190190

191191
#--- unrecognized_ext2.s
@@ -200,7 +200,7 @@
200200
# UNRECOGNIZED_EXT2-NEXT: Attribute {
201201
# UNRECOGNIZED_EXT2-NEXT: Tag: 5
202202
# UNRECOGNIZED_EXT2-NEXT: TagName: arch
203-
# UNRECOGNIZED_EXT2-NEXT: Value: rv64i2p0_zmadeup1p0
203+
# UNRECOGNIZED_EXT2-NEXT: Value: rv64i2p1_zmadeup1p0{{$}}
204204
# UNRECOGNIZED_EXT2-NEXT: }
205205
# UNRECOGNIZED_EXT2-NEXT: }
206206
# UNRECOGNIZED_EXT2-NEXT: }
@@ -213,7 +213,7 @@
213213
.byte 1 # Tag_File
214214
.long .Lend-.Lbegin
215215
.byte 5 # Tag_RISCV_arch
216-
.asciz "rv64i2p0_zmadeup1p0"
216+
.asciz "rv64i2p1_zmadeup1p0"
217217
.Lend:
218218

219219
#--- unrecognized_version.s

‎llvm/docs/ReleaseNotes.rst

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -153,6 +153,9 @@ Changes to the RISC-V Backend
153153
* Assembler support for RV64E was added.
154154
* Assembler support was added for the experimental Zicond (integer conditional
155155
operations) extension.
156+
* I, F, D, and A extension versions have been update to the 20191214 spec versions.
157+
New version I2.1, F2.2, D2.2, A2.1. This should not impact code generation.
158+
Immpacts versions accepted in ``-march`` and reported in ELF attributes.
156159

157160
Changes to the WebAssembly Backend
158161
----------------------------------

‎llvm/lib/Support/RISCVISAInfo.cpp

Lines changed: 16 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -39,13 +39,17 @@ struct RISCVSupportedExtension {
3939

4040
static constexpr StringLiteral AllStdExts = "mafdqlcbkjtpvnh";
4141

42+
static const char *RISCVGImplications[] = {
43+
"i", "m", "a", "f", "d", "zicsr", "zifencei"
44+
};
45+
4246
static const RISCVSupportedExtension SupportedExtensions[] = {
43-
{"i", RISCVExtensionVersion{2, 0}},
47+
{"i", RISCVExtensionVersion{2, 1}},
4448
{"e", RISCVExtensionVersion{2, 0}},
4549
{"m", RISCVExtensionVersion{2, 0}},
46-
{"a", RISCVExtensionVersion{2, 0}},
47-
{"f", RISCVExtensionVersion{2, 0}},
48-
{"d", RISCVExtensionVersion{2, 0}},
50+
{"a", RISCVExtensionVersion{2, 1}},
51+
{"f", RISCVExtensionVersion{2, 2}},
52+
{"d", RISCVExtensionVersion{2, 2}},
4953
{"c", RISCVExtensionVersion{2, 0}},
5054

5155
{"h", RISCVExtensionVersion{1, 0}},
@@ -618,7 +622,7 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool EnableExperimentalExtension,
618622
case 'i':
619623
break;
620624
case 'g':
621-
// g = imafd
625+
// g expands to extensions in RISCVGImplications.
622626
if (Arch.size() > 5 && isDigit(Arch[5]))
623627
return createStringError(errc::invalid_argument,
624628
"version not supported for 'g'");
@@ -652,11 +656,12 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool EnableExperimentalExtension,
652656
// No matter which version is given to `g`, we always set imafd to default
653657
// version since the we don't have clear version scheme for that on
654658
// ISA spec.
655-
for (const auto *Ext : {"i", "m", "a", "f", "d"})
659+
for (const auto *Ext : RISCVGImplications) {
656660
if (auto Version = findDefaultVersion(Ext))
657661
ISAInfo->addExtension(Ext, Version->Major, Version->Minor);
658662
else
659663
llvm_unreachable("Default extension version not found?");
664+
}
660665
} else {
661666
// Baseline is `i` or `e`
662667
if (auto E = getExtensionVersion(
@@ -897,18 +902,20 @@ Error RISCVISAInfo::checkDependency() {
897902
return Error::success();
898903
}
899904

905+
static const char *ImpliedExtsF[] = {"zicsr"};
900906
static const char *ImpliedExtsD[] = {"f"};
901907
static const char *ImpliedExtsV[] = {"zvl128b", "zve64d", "f", "d"};
902908
static const char *ImpliedExtsZfhmin[] = {"f"};
903909
static const char *ImpliedExtsZfh[] = {"f"};
910+
static const char *ImpliedExtsZfinx[] = {"zicsr"};
904911
static const char *ImpliedExtsZdinx[] = {"zfinx"};
905912
static const char *ImpliedExtsZhinxmin[] = {"zfinx"};
906913
static const char *ImpliedExtsZhinx[] = {"zfinx"};
907914
static const char *ImpliedExtsZve64d[] = {"zve64f"};
908915
static const char *ImpliedExtsZve64f[] = {"zve64x", "zve32f"};
909916
static const char *ImpliedExtsZve64x[] = {"zve32x", "zvl64b"};
910917
static const char *ImpliedExtsZve32f[] = {"zve32x"};
911-
static const char *ImpliedExtsZve32x[] = {"zvl32b"};
918+
static const char *ImpliedExtsZve32x[] = {"zvl32b", "zicsr"};
912919
static const char *ImpliedExtsZvl65536b[] = {"zvl32768b"};
913920
static const char *ImpliedExtsZvl32768b[] = {"zvl16384b"};
914921
static const char *ImpliedExtsZvl16384b[] = {"zvl8192b"};
@@ -946,13 +953,15 @@ struct ImpliedExtsEntry {
946953
// Note: The table needs to be sorted by name.
947954
static constexpr ImpliedExtsEntry ImpliedExts[] = {
948955
{{"d"}, {ImpliedExtsD}},
956+
{{"f"}, {ImpliedExtsF}},
949957
{{"v"}, {ImpliedExtsV}},
950958
{{"xtheadvdot"}, {ImpliedExtsXTHeadVdot}},
951959
{{"zcb"}, {ImpliedExtsZcb}},
952960
{{"zdinx"}, {ImpliedExtsZdinx}},
953961
{{"zfa"}, {ImpliedExtsZfa}},
954962
{{"zfh"}, {ImpliedExtsZfh}},
955963
{{"zfhmin"}, {ImpliedExtsZfhmin}},
964+
{{"zfinx"}, {ImpliedExtsZfinx}},
956965
{{"zhinx"}, {ImpliedExtsZhinx}},
957966
{{"zhinxmin"}, {ImpliedExtsZhinxmin}},
958967
{{"zk"}, {ImpliedExtsZk}},

‎llvm/lib/Target/RISCV/RISCVFeatures.td

Lines changed: 12 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -10,6 +10,13 @@
1010
// RISC-V subtarget features and instruction predicates.
1111
//===----------------------------------------------------------------------===//
1212

13+
def FeatureStdExtZicsr
14+
: SubtargetFeature<"zicsr", "HasStdExtZicsr", "true",
15+
"'zicsr' (CSRs)">;
16+
def HasStdExtZicsr : Predicate<"Subtarget->hasStdExtZicsr()">,
17+
AssemblerPredicate<(all_of FeatureStdExtZicsr),
18+
"'Zicsr' (CSRs)">;
19+
1320
def FeatureStdExtM
1421
: SubtargetFeature<"m", "HasStdExtM", "true",
1522
"'M' (Integer Multiplication and Division)">;
@@ -36,7 +43,8 @@ def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">,
3643

3744
def FeatureStdExtF
3845
: SubtargetFeature<"f", "HasStdExtF", "true",
39-
"'F' (Single-Precision Floating-Point)">;
46+
"'F' (Single-Precision Floating-Point)",
47+
[FeatureStdExtZicsr]>;
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def HasStdExtF : Predicate<"Subtarget->hasStdExtF()">,
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AssemblerPredicate<(all_of FeatureStdExtF),
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"'F' (Single-Precision Floating-Point)">;
@@ -71,13 +79,6 @@ def HasStdExtZihintntl : Predicate<"Subtarget->hasStdExtZihintntl()">,
7179
AssemblerPredicate<(all_of FeatureStdExtZihintntl),
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"'Zihintntl' (Non-Temporal Locality Hints)">;
7381

74-
def FeatureStdExtZicsr
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: SubtargetFeature<"zicsr", "HasStdExtZicsr", "true",
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"'zicsr' (CSRs)">;
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def HasStdExtZicsr : Predicate<"Subtarget->hasStdExtZicsr()">,
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AssemblerPredicate<(all_of FeatureStdExtZicsr),
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"'Zicsr' (CSRs)">;
80-
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def FeatureStdExtZifencei
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: SubtargetFeature<"zifencei", "HasStdExtZifencei", "true",
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"'zifencei' (fence.i)">;
@@ -110,7 +111,8 @@ def HasStdExtZfhOrZfhmin
110111

111112
def FeatureStdExtZfinx
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: SubtargetFeature<"zfinx", "HasStdExtZfinx", "true",
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"'Zfinx' (Float in Integer)">;
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"'Zfinx' (Float in Integer)",
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[FeatureStdExtZicsr]>;
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def HasStdExtZfinx : Predicate<"Subtarget->hasStdExtZfinx()">,
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AssemblerPredicate<(all_of FeatureStdExtZfinx),
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"'Zfinx' (Float in Integer)">;
@@ -371,7 +373,7 @@ def FeatureStdExtZve32x
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: SubtargetFeature<"zve32x", "HasStdExtZve32x", "true",
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"'Zve32x' (Vector Extensions for Embedded Processors "
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"with maximal 32 EEW)",
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[FeatureStdExtZvl32b]>;
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[FeatureStdExtZicsr, FeatureStdExtZvl32b]>;
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def FeatureStdExtZve32f
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: SubtargetFeature<"zve32f", "HasStdExtZve32f", "true",

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