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Revert b1234dd. "[DAG] Add legalization handling for ABDS/ABDU (#92576)"
Reverting #92576 while we identify a reported regression
1 parent 97743b8 commit e4e96b3

28 files changed

+4079
-3199
lines changed

‎llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Lines changed: 5 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -4091,13 +4091,13 @@ SDValue DAGCombiner::visitSUB(SDNode *N) {
40914091
}
40924092

40934093
// smax(a,b) - smin(a,b) --> abds(a,b)
4094-
if ((!LegalOperations || hasOperation(ISD::ABDS, VT)) &&
4094+
if (hasOperation(ISD::ABDS, VT) &&
40954095
sd_match(N0, m_SMax(m_Value(A), m_Value(B))) &&
40964096
sd_match(N1, m_SMin(m_Specific(A), m_Specific(B))))
40974097
return DAG.getNode(ISD::ABDS, DL, VT, A, B);
40984098

40994099
// umax(a,b) - umin(a,b) --> abdu(a,b)
4100-
if ((!LegalOperations || hasOperation(ISD::ABDU, VT)) &&
4100+
if (hasOperation(ISD::ABDU, VT) &&
41014101
sd_match(N0, m_UMax(m_Value(A), m_Value(B))) &&
41024102
sd_match(N1, m_UMin(m_Specific(A), m_Specific(B))))
41034103
return DAG.getNode(ISD::ABDU, DL, VT, A, B);
@@ -10924,7 +10924,6 @@ SDValue DAGCombiner::foldABSToABD(SDNode *N, const SDLoc &DL) {
1092410924
(Opc0 != ISD::ZERO_EXTEND && Opc0 != ISD::SIGN_EXTEND &&
1092510925
Opc0 != ISD::SIGN_EXTEND_INREG)) {
1092610926
// fold (abs (sub nsw x, y)) -> abds(x, y)
10927-
// Don't fold this for unsupported types as we lose the NSW handling.
1092810927
if (AbsOp1->getFlags().hasNoSignedWrap() && hasOperation(ISD::ABDS, VT) &&
1092910928
TLI.preferABDSToABSWithNSW(VT)) {
1093010929
SDValue ABD = DAG.getNode(ISD::ABDS, DL, VT, Op0, Op1);
@@ -10947,8 +10946,7 @@ SDValue DAGCombiner::foldABSToABD(SDNode *N, const SDLoc &DL) {
1094710946
// fold abs(zext(x) - zext(y)) -> zext(abdu(x, y))
1094810947
EVT MaxVT = VT0.bitsGT(VT1) ? VT0 : VT1;
1094910948
if ((VT0 == MaxVT || Op0->hasOneUse()) &&
10950-
(VT1 == MaxVT || Op1->hasOneUse()) &&
10951-
(!LegalOperations || hasOperation(ABDOpcode, MaxVT))) {
10949+
(VT1 == MaxVT || Op1->hasOneUse()) && hasOperation(ABDOpcode, MaxVT)) {
1095210950
SDValue ABD = DAG.getNode(ABDOpcode, DL, MaxVT,
1095310951
DAG.getNode(ISD::TRUNCATE, DL, MaxVT, Op0),
1095410952
DAG.getNode(ISD::TRUNCATE, DL, MaxVT, Op1));
@@ -10958,7 +10956,7 @@ SDValue DAGCombiner::foldABSToABD(SDNode *N, const SDLoc &DL) {
1095810956

1095910957
// fold abs(sext(x) - sext(y)) -> abds(sext(x), sext(y))
1096010958
// fold abs(zext(x) - zext(y)) -> abdu(zext(x), zext(y))
10961-
if (!LegalOperations || hasOperation(ABDOpcode, VT)) {
10959+
if (hasOperation(ABDOpcode, VT)) {
1096210960
SDValue ABD = DAG.getNode(ABDOpcode, DL, VT, Op0, Op1);
1096310961
return DAG.getZExtOrTrunc(ABD, DL, SrcVT);
1096410962
}
@@ -11582,7 +11580,7 @@ SDValue DAGCombiner::foldSelectToABD(SDValue LHS, SDValue RHS, SDValue True,
1158211580
unsigned ABDOpc = IsSigned ? ISD::ABDS : ISD::ABDU;
1158311581
EVT VT = LHS.getValueType();
1158411582

11585-
if (LegalOperations && !hasOperation(ABDOpc, VT))
11583+
if (!hasOperation(ABDOpc, VT))
1158611584
return SDValue();
1158711585

1158811586
switch (CC) {

‎llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

Lines changed: 0 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -192,21 +192,17 @@ void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
192192
case ISD::VP_SUB:
193193
case ISD::VP_MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break;
194194

195-
case ISD::ABDS:
196195
case ISD::AVGCEILS:
197196
case ISD::AVGFLOORS:
198-
199197
case ISD::VP_SMIN:
200198
case ISD::VP_SMAX:
201199
case ISD::SDIV:
202200
case ISD::SREM:
203201
case ISD::VP_SDIV:
204202
case ISD::VP_SREM: Res = PromoteIntRes_SExtIntBinOp(N); break;
205203

206-
case ISD::ABDU:
207204
case ISD::AVGCEILU:
208205
case ISD::AVGFLOORU:
209-
210206
case ISD::VP_UMIN:
211207
case ISD::VP_UMAX:
212208
case ISD::UDIV:
@@ -2795,8 +2791,6 @@ void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
27952791
case ISD::PARITY: ExpandIntRes_PARITY(N, Lo, Hi); break;
27962792
case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
27972793
case ISD::ABS: ExpandIntRes_ABS(N, Lo, Hi); break;
2798-
case ISD::ABDS:
2799-
case ISD::ABDU: ExpandIntRes_ABD(N, Lo, Hi); break;
28002794
case ISD::CTLZ_ZERO_UNDEF:
28012795
case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
28022796
case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
@@ -3856,11 +3850,6 @@ void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
38563850
Hi = DAG.getConstant(0, dl, NVT);
38573851
}
38583852

3859-
void DAGTypeLegalizer::ExpandIntRes_ABD(SDNode *N, SDValue &Lo, SDValue &Hi) {
3860-
SDValue Result = TLI.expandABD(N, DAG);
3861-
SplitInteger(Result, Lo, Hi);
3862-
}
3863-
38643853
void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N,
38653854
SDValue &Lo, SDValue &Hi) {
38663855
SDLoc dl(N);

‎llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -448,7 +448,6 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
448448
void ExpandIntRes_AssertZext (SDNode *N, SDValue &Lo, SDValue &Hi);
449449
void ExpandIntRes_Constant (SDNode *N, SDValue &Lo, SDValue &Hi);
450450
void ExpandIntRes_ABS (SDNode *N, SDValue &Lo, SDValue &Hi);
451-
void ExpandIntRes_ABD (SDNode *N, SDValue &Lo, SDValue &Hi);
452451
void ExpandIntRes_CTLZ (SDNode *N, SDValue &Lo, SDValue &Hi);
453452
void ExpandIntRes_CTPOP (SDNode *N, SDValue &Lo, SDValue &Hi);
454453
void ExpandIntRes_CTTZ (SDNode *N, SDValue &Lo, SDValue &Hi);

‎llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -147,8 +147,6 @@ void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
147147
case ISD::FMINIMUM:
148148
case ISD::FMAXIMUM:
149149
case ISD::FLDEXP:
150-
case ISD::ABDS:
151-
case ISD::ABDU:
152150
case ISD::SMIN:
153151
case ISD::SMAX:
154152
case ISD::UMIN:
@@ -1235,8 +1233,6 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
12351233
case ISD::MUL: case ISD::VP_MUL:
12361234
case ISD::MULHS:
12371235
case ISD::MULHU:
1238-
case ISD::ABDS:
1239-
case ISD::ABDU:
12401236
case ISD::AVGCEILS:
12411237
case ISD::AVGCEILU:
12421238
case ISD::AVGFLOORS:
@@ -4372,8 +4368,6 @@ void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
43724368
case ISD::MUL: case ISD::VP_MUL:
43734369
case ISD::MULHS:
43744370
case ISD::MULHU:
4375-
case ISD::ABDS:
4376-
case ISD::ABDU:
43774371
case ISD::OR: case ISD::VP_OR:
43784372
case ISD::SUB: case ISD::VP_SUB:
43794373
case ISD::XOR: case ISD::VP_XOR:

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -7024,8 +7024,6 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
70247024
assert(VT.isInteger() && "This operator does not apply to FP types!");
70257025
assert(N1.getValueType() == N2.getValueType() &&
70267026
N1.getValueType() == VT && "Binary operator types must match!");
7027-
if (VT.isVector() && VT.getVectorElementType() == MVT::i1)
7028-
return getNode(ISD::XOR, DL, VT, N1, N2);
70297027
break;
70307028
case ISD::SMIN:
70317029
case ISD::UMAX:

‎llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

Lines changed: 0 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -9311,21 +9311,6 @@ SDValue TargetLowering::expandABD(SDNode *N, SelectionDAG &DAG) const {
93119311
DAG.getNode(ISD::USUBSAT, dl, VT, LHS, RHS),
93129312
DAG.getNode(ISD::USUBSAT, dl, VT, RHS, LHS));
93139313

9314-
// If the subtract doesn't overflow then just use abs(sub())
9315-
// NOTE: don't use frozen operands for value tracking.
9316-
bool IsNonNegative = DAG.SignBitIsZero(N->getOperand(1)) &&
9317-
DAG.SignBitIsZero(N->getOperand(0));
9318-
9319-
if (DAG.willNotOverflowSub(IsSigned || IsNonNegative, N->getOperand(0),
9320-
N->getOperand(1)))
9321-
return DAG.getNode(ISD::ABS, dl, VT,
9322-
DAG.getNode(ISD::SUB, dl, VT, LHS, RHS));
9323-
9324-
if (DAG.willNotOverflowSub(IsSigned || IsNonNegative, N->getOperand(1),
9325-
N->getOperand(0)))
9326-
return DAG.getNode(ISD::ABS, dl, VT,
9327-
DAG.getNode(ISD::SUB, dl, VT, RHS, LHS));
9328-
93299314
EVT CCVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
93309315
ISD::CondCode CC = IsSigned ? ISD::CondCode::SETGT : ISD::CondCode::SETUGT;
93319316
SDValue Cmp = DAG.getSetCC(dl, CCVT, LHS, RHS, CC);
@@ -9339,23 +9324,6 @@ SDValue TargetLowering::expandABD(SDNode *N, SelectionDAG &DAG) const {
93399324
return DAG.getNode(ISD::SUB, dl, VT, Cmp, Xor);
93409325
}
93419326

9342-
// Similar to the branchless expansion, use the (sign-extended) usubo overflow
9343-
// flag if the (scalar) type is illegal as this is more likely to legalize
9344-
// cleanly:
9345-
// abdu(lhs, rhs) -> sub(xor(sub(lhs, rhs), uof(lhs, rhs)), uof(lhs, rhs))
9346-
if (!IsSigned && VT.isScalarInteger() && !isTypeLegal(VT)) {
9347-
SDValue USubO =
9348-
DAG.getNode(ISD::USUBO, dl, DAG.getVTList(VT, MVT::i1), {LHS, RHS});
9349-
SDValue Cmp = DAG.getNode(ISD::SIGN_EXTEND, dl, VT, USubO.getValue(1));
9350-
SDValue Xor = DAG.getNode(ISD::XOR, dl, VT, USubO.getValue(0), Cmp);
9351-
return DAG.getNode(ISD::SUB, dl, VT, Xor, Cmp);
9352-
}
9353-
9354-
// FIXME: Should really try to split the vector in case it's legal on a
9355-
// subvector.
9356-
if (VT.isVector() && !isOperationLegalOrCustom(ISD::VSELECT, VT))
9357-
return DAG.UnrollVectorOp(N);
9358-
93599327
// abds(lhs, rhs) -> select(sgt(lhs,rhs), sub(lhs,rhs), sub(rhs,lhs))
93609328
// abdu(lhs, rhs) -> select(ugt(lhs,rhs), sub(lhs,rhs), sub(rhs,lhs))
93619329
return DAG.getSelect(dl, VT, Cmp, DAG.getNode(ISD::SUB, dl, VT, LHS, RHS),

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