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4 files changed

+63
-51
lines changed

‎llvm/lib/Target/AArch64/AArch64FrameLowering.cpp

+35-38
Original file line numberDiff line numberDiff line change
@@ -4208,7 +4208,7 @@ struct ScopedScavengeOrSpill {
42084208
ScopedScavengeOrSpill(ScopedScavengeOrSpill &&) = delete;
42094209

42104210
ScopedScavengeOrSpill(MachineFunction &MF, MachineBasicBlock &MBB,
4211-
MachineBasicBlock::iterator MBBI, Register &FreeReg,
4211+
MachineBasicBlock::iterator MBBI,
42124212
Register SpillCandidate, const TargetRegisterClass &RC,
42134213
LiveRegUnits const &UsedRegs,
42144214
BitVector const &AllocatableRegs,
@@ -4226,17 +4226,22 @@ struct ScopedScavengeOrSpill {
42264226
*MaybeSpillFI = MFI.CreateSpillStackObject(TRI.getSpillSize(RC),
42274227
TRI.getSpillAlign(RC));
42284228
}
4229-
FreeReg = SpilledReg = SpillCandidate;
4229+
FreeReg = SpillCandidate;
42304230
SpillFI = MaybeSpillFI->value();
4231-
TII.storeRegToStackSlot(MBB, MBBI, SpilledReg, false, SpillFI, &RC, &TRI,
4231+
TII.storeRegToStackSlot(MBB, MBBI, FreeReg, false, *SpillFI, &RC, &TRI,
42324232
Register());
42334233
}
42344234

4235-
bool hasSpilled() const { return SpilledReg != AArch64::NoRegister; }
4235+
bool hasSpilled() const { return SpillFI.has_value(); }
4236+
4237+
/// Returns the free register (found from scavenging or spilling a register).
4238+
Register freeRegister() const { return FreeReg; }
4239+
4240+
Register operator*() const { return freeRegister(); }
42364241

42374242
~ScopedScavengeOrSpill() {
42384243
if (hasSpilled())
4239-
TII.loadRegFromStackSlot(MBB, MBBI, SpilledReg, SpillFI, &RC, &TRI,
4244+
TII.loadRegFromStackSlot(MBB, MBBI, FreeReg, *SpillFI, &RC, &TRI,
42404245
Register());
42414246
}
42424247

@@ -4246,8 +4251,8 @@ struct ScopedScavengeOrSpill {
42464251
const TargetRegisterClass &RC;
42474252
const AArch64InstrInfo &TII;
42484253
const TargetRegisterInfo &TRI;
4249-
Register SpilledReg = AArch64::NoRegister;
4250-
int SpillFI = -1;
4254+
Register FreeReg = AArch64::NoRegister;
4255+
std::optional<int> SpillFI;
42514256
};
42524257

42534258
/// Emergency stack slots for expanding SPILL_PPR_TO_ZPR_SLOT_PSEUDO and
@@ -4291,22 +4296,20 @@ static void expandSpillPPRToZPRSlotPseudo(MachineBasicBlock &MBB,
42914296
auto *TII =
42924297
static_cast<const AArch64InstrInfo *>(MF.getSubtarget().getInstrInfo());
42934298

4294-
Register ZPredReg = AArch64::NoRegister;
4295-
ScopedScavengeOrSpill FindZPRReg(
4296-
MF, MBB, MachineBasicBlock::iterator(MI), ZPredReg, AArch64::Z0,
4297-
AArch64::ZPRRegClass, UsedRegs, SR.ZPRRegs,
4299+
ScopedScavengeOrSpill ZPredReg(
4300+
MF, MBB, MI, AArch64::Z0, AArch64::ZPRRegClass, UsedRegs, SR.ZPRRegs,
42984301
isInPrologueOrEpilogue(MI) ? nullptr : &SpillSlots.ZPRSpillFI);
42994302

43004303
SmallVector<MachineInstr *, 2> MachineInstrs;
43014304
const DebugLoc &DL = MI.getDebugLoc();
43024305
MachineInstrs.push_back(BuildMI(MBB, MI, DL, TII->get(AArch64::CPY_ZPzI_B))
4303-
.addReg(ZPredReg, RegState::Define)
4306+
.addReg(*ZPredReg, RegState::Define)
43044307
.add(MI.getOperand(0))
43054308
.addImm(1)
43064309
.addImm(0)
43074310
.getInstr());
43084311
MachineInstrs.push_back(BuildMI(MBB, MI, DL, TII->get(AArch64::STR_ZXI))
4309-
.addReg(ZPredReg)
4312+
.addReg(*ZPredReg)
43104313
.add(MI.getOperand(1))
43114314
.addImm(MI.getOperand(2).getImm())
43124315
.setMemRefs(MI.memoperands())
@@ -4338,61 +4341,56 @@ static bool expandFillPPRFromZPRSlotPseudo(MachineBasicBlock &MBB,
43384341
auto *TII =
43394342
static_cast<const AArch64InstrInfo *>(MF.getSubtarget().getInstrInfo());
43404343

4341-
Register ZPredReg = AArch64::NoRegister;
4342-
ScopedScavengeOrSpill FindZPRReg(
4343-
MF, MBB, MachineBasicBlock::iterator(MI), ZPredReg, AArch64::Z0,
4344-
AArch64::ZPRRegClass, UsedRegs, SR.ZPRRegs,
4344+
ScopedScavengeOrSpill ZPredReg(
4345+
MF, MBB, MI, AArch64::Z0, AArch64::ZPRRegClass, UsedRegs, SR.ZPRRegs,
43454346
isInPrologueOrEpilogue(MI) ? nullptr : &SpillSlots.ZPRSpillFI);
43464347

4347-
Register PredReg = AArch64::NoRegister;
4348-
ScopedScavengeOrSpill FindPPR3bReg(
4349-
MF, MBB, MachineBasicBlock::iterator(MI), PredReg, AArch64::P0,
4350-
AArch64::PPR_3bRegClass, UsedRegs, SR.PPR3bRegs,
4348+
ScopedScavengeOrSpill PredReg(
4349+
MF, MBB, MI, AArch64::P0, AArch64::PPR_3bRegClass, UsedRegs, SR.PPR3bRegs,
43514350
isInPrologueOrEpilogue(MI) ? nullptr : &SpillSlots.PPRSpillFI);
43524351

43534352
// Elide NZCV spills if we know it is not used.
4354-
Register NZCVSaveReg = AArch64::NoRegister;
43554353
bool IsNZCVUsed = !UsedRegs.available(AArch64::NZCV);
4356-
std::optional<ScopedScavengeOrSpill> FindGPRReg;
4354+
std::optional<ScopedScavengeOrSpill> NZCVSaveReg;
43574355
if (IsNZCVUsed)
4358-
FindGPRReg.emplace(
4359-
MF, MBB, MachineBasicBlock::iterator(MI), NZCVSaveReg, AArch64::X0,
4360-
AArch64::GPR64RegClass, UsedRegs, SR.GPRRegs,
4356+
NZCVSaveReg.emplace(
4357+
MF, MBB, MI, AArch64::X0, AArch64::GPR64RegClass, UsedRegs, SR.GPRRegs,
43614358
isInPrologueOrEpilogue(MI) ? nullptr : &SpillSlots.GPRSpillFI);
43624359
SmallVector<MachineInstr *, 4> MachineInstrs;
43634360
const DebugLoc &DL = MI.getDebugLoc();
43644361
MachineInstrs.push_back(BuildMI(MBB, MI, DL, TII->get(AArch64::LDR_ZXI))
4365-
.addReg(ZPredReg, RegState::Define)
4362+
.addReg(*ZPredReg, RegState::Define)
43664363
.add(MI.getOperand(1))
43674364
.addImm(MI.getOperand(2).getImm())
43684365
.setMemRefs(MI.memoperands())
43694366
.getInstr());
43704367
if (IsNZCVUsed)
4371-
MachineInstrs.push_back(BuildMI(MBB, MI, DL, TII->get(AArch64::MRS))
4372-
.addReg(NZCVSaveReg, RegState::Define)
4373-
.addImm(AArch64SysReg::NZCV)
4374-
.addReg(AArch64::NZCV, RegState::Implicit)
4375-
.getInstr());
4368+
MachineInstrs.push_back(
4369+
BuildMI(MBB, MI, DL, TII->get(AArch64::MRS))
4370+
.addReg(NZCVSaveReg->freeRegister(), RegState::Define)
4371+
.addImm(AArch64SysReg::NZCV)
4372+
.addReg(AArch64::NZCV, RegState::Implicit)
4373+
.getInstr());
43764374
MachineInstrs.push_back(BuildMI(MBB, MI, DL, TII->get(AArch64::PTRUE_B))
4377-
.addReg(PredReg, RegState::Define)
4375+
.addReg(*PredReg, RegState::Define)
43784376
.addImm(31));
43794377
MachineInstrs.push_back(
43804378
BuildMI(MBB, MI, DL, TII->get(AArch64::CMPNE_PPzZI_B))
43814379
.addReg(MI.getOperand(0).getReg(), RegState::Define)
4382-
.addReg(PredReg)
4383-
.addReg(ZPredReg)
4380+
.addReg(*PredReg)
4381+
.addReg(*ZPredReg)
43844382
.addImm(0)
43854383
.addReg(AArch64::NZCV, RegState::ImplicitDefine)
43864384
.getInstr());
43874385
if (IsNZCVUsed)
43884386
MachineInstrs.push_back(BuildMI(MBB, MI, DL, TII->get(AArch64::MSR))
43894387
.addImm(AArch64SysReg::NZCV)
4390-
.addReg(NZCVSaveReg)
4388+
.addReg(NZCVSaveReg->freeRegister())
43914389
.addReg(AArch64::NZCV, RegState::ImplicitDefine)
43924390
.getInstr());
43934391

43944392
propagateFrameFlags(MI, MachineInstrs);
4395-
return FindPPR3bReg.hasSpilled();
4393+
return PredReg.hasSpilled();
43964394
}
43974395

43984396
/// Expands all FILL_PPR_FROM_ZPR_SLOT_PSEUDO and SPILL_PPR_TO_ZPR_SLOT_PSEUDO
@@ -5510,7 +5508,6 @@ void AArch64FrameLowering::emitRemarks(
55105508
if (MI.getOpcode() != AArch64::SPILL_PPR_TO_ZPR_SLOT_PSEUDO &&
55115509
MI.getOpcode() != AArch64::FILL_PPR_FROM_ZPR_SLOT_PSEUDO &&
55125510
AArch64::PPRRegClass.contains(MI.getOperand(0).getReg())) {
5513-
MI.dump();
55145511
RegTy = StackAccess::PPR;
55155512
} else
55165513
RegTy = StackAccess::FPR;

‎llvm/lib/Target/AArch64/AArch64RegisterInfo.td

+2-2
Original file line numberDiff line numberDiff line change
@@ -982,10 +982,10 @@ class ZPRRegOp <string Suffix, AsmOperandClass C, ElementSizeEnum Size,
982982

983983
// Note: This hardware mode is enabled in AArch64Subtarget::getHwModeSet()
984984
// (without the use of the table-gen'd predicates).
985-
def SMEWithStreamingMemoryHazards : HwMode<"", [Predicate<"false">]>;
985+
def SMEWithZPRPredicateSpills : HwMode<"", [Predicate<"false">]>;
986986

987987
def PPRSpillFillRI : RegInfoByHwMode<
988-
[DefaultMode, SMEWithStreamingMemoryHazards],
988+
[DefaultMode, SMEWithZPRPredicateSpills],
989989
[RegInfo<16,16,16>, RegInfo<16,128,128>]>;
990990

991991
class PPRClass<int firstreg, int lastreg, int step = 1> : RegisterClass<"AArch64",

‎llvm/lib/Target/AArch64/AArch64Subtarget.cpp

+5-10
Original file line numberDiff line numberDiff line change
@@ -406,20 +406,15 @@ AArch64Subtarget::AArch64Subtarget(const Triple &TT, StringRef CPU,
406406
}
407407

408408
unsigned AArch64Subtarget::getHwModeSet() const {
409-
unsigned Modes = 0;
410-
411-
// Use a special hardware mode in streaming functions with stack hazards.
412-
// This changes the spill size (and alignment) for the predicate register
413-
// class.
414-
//
415-
// FIXME: This overrides the table-gen'd `getHwModeSet()` which only looks at
416-
// CPU features.
409+
// Use a special hardware mode in streaming[-compatible] functions with
410+
// aarch64-enable-zpr-predicate-spills. This changes the spill size (and
411+
// alignment) for the predicate register class.
417412
if (EnableZPRPredicateSpills.getValue() &&
418413
(isStreaming() || isStreamingCompatible())) {
419-
Modes |= (1 << 0);
414+
return to_underlying(AArch64HwModeBits::SMEWithZPRPredicateSpills);
420415
}
421416

422-
return Modes;
417+
return to_underlying(AArch64HwModeBits::DefaultMode);
423418
}
424419

425420
const CallLowering *AArch64Subtarget::getCallLowering() const {

‎llvm/utils/TableGen/SubtargetEmitter.cpp

+21-1
Original file line numberDiff line numberDiff line change
@@ -2082,6 +2082,7 @@ void SubtargetEmitter::run(raw_ostream &OS) {
20822082
OS << "\n#ifdef GET_SUBTARGETINFO_TARGET_DESC\n";
20832083
OS << "#undef GET_SUBTARGETINFO_TARGET_DESC\n\n";
20842084

2085+
OS << "#include \"llvm/ADT/BitmaskEnum.h\"\n";
20852086
OS << "#include \"llvm/Support/Debug.h\"\n";
20862087
OS << "#include \"llvm/Support/raw_ostream.h\"\n\n";
20872088
if (Target == "AArch64")
@@ -2113,7 +2114,26 @@ void SubtargetEmitter::run(raw_ostream &OS) {
21132114
<< " unsigned CPUID) const override;\n"
21142115
<< " DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID)"
21152116
<< " const;\n";
2116-
if (TGT.getHwModes().getNumModeIds() > 1) {
2117+
2118+
const CodeGenHwModes &CGH = TGT.getHwModes();
2119+
if (CGH.getNumModeIds() > 1) {
2120+
OS << " enum class " << Target << "HwModeBits : unsigned {\n";
2121+
for (unsigned M = 0, NumModes = CGH.getNumModeIds(); M != NumModes; ++M) {
2122+
StringRef ModeName = CGH.getModeName(M, /*IncludeDefault=*/true);
2123+
OS << " " << ModeName << " = ";
2124+
if (M == CodeGenHwModes::DefaultMode)
2125+
OS << "0";
2126+
else
2127+
OS << "(1 << " << (M - 1) << ")";
2128+
OS << ",\n";
2129+
if (M == NumModes - 1) {
2130+
OS << "\n";
2131+
OS << " LLVM_MARK_AS_BITMASK_ENUM(/*LargestValue=*/" << ModeName
2132+
<< "),\n";
2133+
}
2134+
}
2135+
OS << " };\n";
2136+
21172137
OS << " unsigned getHwModeSet() const override;\n";
21182138
OS << " unsigned getHwMode(enum HwModeType type = HwMode_Default) const "
21192139
"override;\n";

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