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[RISCV] Move RISCVVType namespace to TargetParser
Clang and some middle-end optimizations may need these helper functions. This can reduce some duplications.
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8 files changed

+173
-165
lines changed

8 files changed

+173
-165
lines changed

‎llvm/include/llvm/TargetParser/RISCVTargetParser.h

Lines changed: 77 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,8 @@
1515
#define LLVM_TARGETPARSER_RISCVTARGETPARSER_H
1616

1717
#include "llvm/ADT/StringRef.h"
18+
#include "llvm/Support/MathExtras.h"
19+
#include "llvm/Support/raw_ostream.h"
1820

1921
namespace llvm {
2022

@@ -33,6 +35,81 @@ void fillValidTuneCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64);
3335
bool hasFastUnalignedAccess(StringRef CPU);
3436

3537
} // namespace RISCV
38+
39+
namespace RISCVII {
40+
enum VLMUL : uint8_t {
41+
LMUL_1 = 0,
42+
LMUL_2,
43+
LMUL_4,
44+
LMUL_8,
45+
LMUL_RESERVED,
46+
LMUL_F8,
47+
LMUL_F4,
48+
LMUL_F2
49+
};
50+
51+
enum {
52+
TAIL_UNDISTURBED_MASK_UNDISTURBED = 0,
53+
TAIL_AGNOSTIC = 1,
54+
MASK_AGNOSTIC = 2,
55+
};
56+
} // namespace RISCVII
57+
58+
namespace RISCVVType {
59+
// Is this a SEW value that can be encoded into the VTYPE format.
60+
inline static bool isValidSEW(unsigned SEW) {
61+
return isPowerOf2_32(SEW) && SEW >= 8 && SEW <= 1024;
62+
}
63+
64+
// Is this a LMUL value that can be encoded into the VTYPE format.
65+
inline static bool isValidLMUL(unsigned LMUL, bool Fractional) {
66+
return isPowerOf2_32(LMUL) && LMUL <= 8 && (!Fractional || LMUL != 1);
67+
}
68+
69+
unsigned encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic,
70+
bool MaskAgnostic);
71+
72+
inline static RISCVII::VLMUL getVLMUL(unsigned VType) {
73+
unsigned VLMUL = VType & 0x7;
74+
return static_cast<RISCVII::VLMUL>(VLMUL);
75+
}
76+
77+
// Decode VLMUL into 1,2,4,8 and fractional indicator.
78+
std::pair<unsigned, bool> decodeVLMUL(RISCVII::VLMUL VLMUL);
79+
80+
inline static RISCVII::VLMUL encodeLMUL(unsigned LMUL, bool Fractional) {
81+
assert(isValidLMUL(LMUL, Fractional) && "Unsupported LMUL");
82+
unsigned LmulLog2 = Log2_32(LMUL);
83+
return static_cast<RISCVII::VLMUL>(Fractional ? 8 - LmulLog2 : LmulLog2);
84+
}
85+
86+
inline static unsigned decodeVSEW(unsigned VSEW) {
87+
assert(VSEW < 8 && "Unexpected VSEW value");
88+
return 1 << (VSEW + 3);
89+
}
90+
91+
inline static unsigned encodeSEW(unsigned SEW) {
92+
assert(isValidSEW(SEW) && "Unexpected SEW value");
93+
return Log2_32(SEW) - 3;
94+
}
95+
96+
inline static unsigned getSEW(unsigned VType) {
97+
unsigned VSEW = (VType >> 3) & 0x7;
98+
return decodeVSEW(VSEW);
99+
}
100+
101+
inline static bool isTailAgnostic(unsigned VType) { return VType & 0x40; }
102+
103+
inline static bool isMaskAgnostic(unsigned VType) { return VType & 0x80; }
104+
105+
void printVType(unsigned VType, raw_ostream &OS);
106+
107+
unsigned getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul);
108+
109+
std::optional<RISCVII::VLMUL>
110+
getSameRatioLMUL(unsigned SEW, RISCVII::VLMUL VLMUL, unsigned EEW);
111+
} // namespace RISCVVType
112+
36113
} // namespace llvm
37114

38115
#endif

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp

Lines changed: 0 additions & 87 deletions
Original file line numberDiff line numberDiff line change
@@ -134,93 +134,6 @@ parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits) {
134134

135135
} // namespace RISCVFeatures
136136

137-
// Encode VTYPE into the binary format used by the the VSETVLI instruction which
138-
// is used by our MC layer representation.
139-
//
140-
// Bits | Name | Description
141-
// -----+------------+------------------------------------------------
142-
// 7 | vma | Vector mask agnostic
143-
// 6 | vta | Vector tail agnostic
144-
// 5:3 | vsew[2:0] | Standard element width (SEW) setting
145-
// 2:0 | vlmul[2:0] | Vector register group multiplier (LMUL) setting
146-
unsigned RISCVVType::encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW,
147-
bool TailAgnostic, bool MaskAgnostic) {
148-
assert(isValidSEW(SEW) && "Invalid SEW");
149-
unsigned VLMULBits = static_cast<unsigned>(VLMUL);
150-
unsigned VSEWBits = encodeSEW(SEW);
151-
unsigned VTypeI = (VSEWBits << 3) | (VLMULBits & 0x7);
152-
if (TailAgnostic)
153-
VTypeI |= 0x40;
154-
if (MaskAgnostic)
155-
VTypeI |= 0x80;
156-
157-
return VTypeI;
158-
}
159-
160-
std::pair<unsigned, bool> RISCVVType::decodeVLMUL(RISCVII::VLMUL VLMUL) {
161-
switch (VLMUL) {
162-
default:
163-
llvm_unreachable("Unexpected LMUL value!");
164-
case RISCVII::VLMUL::LMUL_1:
165-
case RISCVII::VLMUL::LMUL_2:
166-
case RISCVII::VLMUL::LMUL_4:
167-
case RISCVII::VLMUL::LMUL_8:
168-
return std::make_pair(1 << static_cast<unsigned>(VLMUL), false);
169-
case RISCVII::VLMUL::LMUL_F2:
170-
case RISCVII::VLMUL::LMUL_F4:
171-
case RISCVII::VLMUL::LMUL_F8:
172-
return std::make_pair(1 << (8 - static_cast<unsigned>(VLMUL)), true);
173-
}
174-
}
175-
176-
void RISCVVType::printVType(unsigned VType, raw_ostream &OS) {
177-
unsigned Sew = getSEW(VType);
178-
OS << "e" << Sew;
179-
180-
unsigned LMul;
181-
bool Fractional;
182-
std::tie(LMul, Fractional) = decodeVLMUL(getVLMUL(VType));
183-
184-
if (Fractional)
185-
OS << ", mf";
186-
else
187-
OS << ", m";
188-
OS << LMul;
189-
190-
if (isTailAgnostic(VType))
191-
OS << ", ta";
192-
else
193-
OS << ", tu";
194-
195-
if (isMaskAgnostic(VType))
196-
OS << ", ma";
197-
else
198-
OS << ", mu";
199-
}
200-
201-
unsigned RISCVVType::getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul) {
202-
unsigned LMul;
203-
bool Fractional;
204-
std::tie(LMul, Fractional) = decodeVLMUL(VLMul);
205-
206-
// Convert LMul to a fixed point value with 3 fractional bits.
207-
LMul = Fractional ? (8 / LMul) : (LMul * 8);
208-
209-
assert(SEW >= 8 && "Unexpected SEW value");
210-
return (SEW * 8) / LMul;
211-
}
212-
213-
std::optional<RISCVII::VLMUL>
214-
RISCVVType::getSameRatioLMUL(unsigned SEW, RISCVII::VLMUL VLMUL, unsigned EEW) {
215-
unsigned Ratio = RISCVVType::getSEWLMULRatio(SEW, VLMUL);
216-
unsigned EMULFixedPoint = (EEW * 8) / Ratio;
217-
bool Fractional = EMULFixedPoint < 8;
218-
unsigned EMUL = Fractional ? 8 / EMULFixedPoint : EMULFixedPoint / 8;
219-
if (!isValidLMUL(EMUL, Fractional))
220-
return std::nullopt;
221-
return RISCVVType::encodeLMUL(EMUL, Fractional);
222-
}
223-
224137
// Include the auto-generated portion of the compress emitter.
225138
#define GEN_UNCOMPRESS_INSTR
226139
#define GEN_COMPRESS_INSTR

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

Lines changed: 1 addition & 72 deletions
Original file line numberDiff line numberDiff line change
@@ -20,6 +20,7 @@
2020
#include "llvm/ADT/StringSwitch.h"
2121
#include "llvm/MC/MCInstrDesc.h"
2222
#include "llvm/Support/RISCVISAInfo.h"
23+
#include "llvm/TargetParser/RISCVTargetParser.h"
2324
#include "llvm/TargetParser/SubtargetFeature.h"
2425

2526
namespace llvm {
@@ -124,23 +125,6 @@ enum {
124125
TargetOverlapConstraintTypeMask = 3ULL << TargetOverlapConstraintTypeShift,
125126
};
126127

127-
enum VLMUL : uint8_t {
128-
LMUL_1 = 0,
129-
LMUL_2,
130-
LMUL_4,
131-
LMUL_8,
132-
LMUL_RESERVED,
133-
LMUL_F8,
134-
LMUL_F4,
135-
LMUL_F2
136-
};
137-
138-
enum {
139-
TAIL_UNDISTURBED_MASK_UNDISTURBED = 0,
140-
TAIL_AGNOSTIC = 1,
141-
MASK_AGNOSTIC = 2,
142-
};
143-
144128
// Helper functions to read TSFlags.
145129
/// \returns the format of the instruction.
146130
static inline unsigned getFormat(uint64_t TSFlags) {
@@ -484,61 +468,6 @@ parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits);
484468

485469
} // namespace RISCVFeatures
486470

487-
namespace RISCVVType {
488-
// Is this a SEW value that can be encoded into the VTYPE format.
489-
inline static bool isValidSEW(unsigned SEW) {
490-
return isPowerOf2_32(SEW) && SEW >= 8 && SEW <= 1024;
491-
}
492-
493-
// Is this a LMUL value that can be encoded into the VTYPE format.
494-
inline static bool isValidLMUL(unsigned LMUL, bool Fractional) {
495-
return isPowerOf2_32(LMUL) && LMUL <= 8 && (!Fractional || LMUL != 1);
496-
}
497-
498-
unsigned encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic,
499-
bool MaskAgnostic);
500-
501-
inline static RISCVII::VLMUL getVLMUL(unsigned VType) {
502-
unsigned VLMUL = VType & 0x7;
503-
return static_cast<RISCVII::VLMUL>(VLMUL);
504-
}
505-
506-
// Decode VLMUL into 1,2,4,8 and fractional indicator.
507-
std::pair<unsigned, bool> decodeVLMUL(RISCVII::VLMUL VLMUL);
508-
509-
inline static RISCVII::VLMUL encodeLMUL(unsigned LMUL, bool Fractional) {
510-
assert(isValidLMUL(LMUL, Fractional) && "Unsupported LMUL");
511-
unsigned LmulLog2 = Log2_32(LMUL);
512-
return static_cast<RISCVII::VLMUL>(Fractional ? 8 - LmulLog2 : LmulLog2);
513-
}
514-
515-
inline static unsigned decodeVSEW(unsigned VSEW) {
516-
assert(VSEW < 8 && "Unexpected VSEW value");
517-
return 1 << (VSEW + 3);
518-
}
519-
520-
inline static unsigned encodeSEW(unsigned SEW) {
521-
assert(isValidSEW(SEW) && "Unexpected SEW value");
522-
return Log2_32(SEW) - 3;
523-
}
524-
525-
inline static unsigned getSEW(unsigned VType) {
526-
unsigned VSEW = (VType >> 3) & 0x7;
527-
return decodeVSEW(VSEW);
528-
}
529-
530-
inline static bool isTailAgnostic(unsigned VType) { return VType & 0x40; }
531-
532-
inline static bool isMaskAgnostic(unsigned VType) { return VType & 0x80; }
533-
534-
void printVType(unsigned VType, raw_ostream &OS);
535-
536-
unsigned getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul);
537-
538-
std::optional<RISCVII::VLMUL>
539-
getSameRatioLMUL(unsigned SEW, RISCVII::VLMUL VLMUL, unsigned EEW);
540-
} // namespace RISCVVType
541-
542471
namespace RISCVRVC {
543472
bool compress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI);
544473
bool uncompress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI);

‎llvm/lib/Target/RISCV/RISCVISelLowering.h

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,6 @@
1818
#include "llvm/CodeGen/CallingConvLower.h"
1919
#include "llvm/CodeGen/SelectionDAG.h"
2020
#include "llvm/CodeGen/TargetLowering.h"
21-
#include "llvm/TargetParser/RISCVTargetParser.h"
2221
#include <optional>
2322

2423
namespace llvm {

‎llvm/lib/TargetParser/RISCVTargetParser.cpp

Lines changed: 91 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -96,4 +96,95 @@ void fillValidTuneCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64) {
9696
}
9797

9898
} // namespace RISCV
99+
100+
namespace RISCVVType {
101+
// Encode VTYPE into the binary format used by the the VSETVLI instruction which
102+
// is used by our MC layer representation.
103+
//
104+
// Bits | Name | Description
105+
// -----+------------+------------------------------------------------
106+
// 7 | vma | Vector mask agnostic
107+
// 6 | vta | Vector tail agnostic
108+
// 5:3 | vsew[2:0] | Standard element width (SEW) setting
109+
// 2:0 | vlmul[2:0] | Vector register group multiplier (LMUL) setting
110+
unsigned encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic,
111+
bool MaskAgnostic) {
112+
assert(isValidSEW(SEW) && "Invalid SEW");
113+
unsigned VLMULBits = static_cast<unsigned>(VLMUL);
114+
unsigned VSEWBits = encodeSEW(SEW);
115+
unsigned VTypeI = (VSEWBits << 3) | (VLMULBits & 0x7);
116+
if (TailAgnostic)
117+
VTypeI |= 0x40;
118+
if (MaskAgnostic)
119+
VTypeI |= 0x80;
120+
121+
return VTypeI;
122+
}
123+
124+
std::pair<unsigned, bool> decodeVLMUL(RISCVII::VLMUL VLMUL) {
125+
switch (VLMUL) {
126+
default:
127+
llvm_unreachable("Unexpected LMUL value!");
128+
case RISCVII::VLMUL::LMUL_1:
129+
case RISCVII::VLMUL::LMUL_2:
130+
case RISCVII::VLMUL::LMUL_4:
131+
case RISCVII::VLMUL::LMUL_8:
132+
return std::make_pair(1 << static_cast<unsigned>(VLMUL), false);
133+
case RISCVII::VLMUL::LMUL_F2:
134+
case RISCVII::VLMUL::LMUL_F4:
135+
case RISCVII::VLMUL::LMUL_F8:
136+
return std::make_pair(1 << (8 - static_cast<unsigned>(VLMUL)), true);
137+
}
138+
}
139+
140+
void printVType(unsigned VType, raw_ostream &OS) {
141+
unsigned Sew = getSEW(VType);
142+
OS << "e" << Sew;
143+
144+
unsigned LMul;
145+
bool Fractional;
146+
std::tie(LMul, Fractional) = decodeVLMUL(getVLMUL(VType));
147+
148+
if (Fractional)
149+
OS << ", mf";
150+
else
151+
OS << ", m";
152+
OS << LMul;
153+
154+
if (isTailAgnostic(VType))
155+
OS << ", ta";
156+
else
157+
OS << ", tu";
158+
159+
if (isMaskAgnostic(VType))
160+
OS << ", ma";
161+
else
162+
OS << ", mu";
163+
}
164+
165+
unsigned getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul) {
166+
unsigned LMul;
167+
bool Fractional;
168+
std::tie(LMul, Fractional) = decodeVLMUL(VLMul);
169+
170+
// Convert LMul to a fixed point value with 3 fractional bits.
171+
LMul = Fractional ? (8 / LMul) : (LMul * 8);
172+
173+
assert(SEW >= 8 && "Unexpected SEW value");
174+
return (SEW * 8) / LMul;
175+
}
176+
177+
std::optional<RISCVII::VLMUL>
178+
getSameRatioLMUL(unsigned SEW, RISCVII::VLMUL VLMUL, unsigned EEW) {
179+
unsigned Ratio = RISCVVType::getSEWLMULRatio(SEW, VLMUL);
180+
unsigned EMULFixedPoint = (EEW * 8) / Ratio;
181+
bool Fractional = EMULFixedPoint < 8;
182+
unsigned EMUL = Fractional ? 8 / EMULFixedPoint : EMULFixedPoint / 8;
183+
if (!isValidLMUL(EMUL, Fractional))
184+
return std::nullopt;
185+
return RISCVVType::encodeLMUL(EMUL, Fractional);
186+
}
187+
188+
} // namespace RISCVVType
189+
99190
} // namespace llvm

‎llvm/unittests/Target/RISCV/CMakeLists.txt

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,6 @@ set(LLVM_LINK_COMPONENTS
1616

1717
add_llvm_target_unittest(RISCVTests
1818
MCInstrAnalysisTest.cpp
19-
RISCVBaseInfoTest.cpp
2019
RISCVInstrInfoTest.cpp
2120
)
2221

‎llvm/unittests/TargetParser/CMakeLists.txt

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,7 @@ add_llvm_unittest(TargetParserTests
88
Host.cpp
99
TargetParserTest.cpp
1010
TripleTest.cpp
11+
RISCVTargetParserTest.cpp
1112
)
1213

1314
target_link_libraries(TargetParserTests PRIVATE LLVMTestingSupport)

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